9  EP 1 499 943 B1 10  to the highest level of performance  204 . However, the processing load may not increased thus decreasing the actualpercent CPUutilization  201  from,forexample 50% to 48% CPU utilization  201 . In one embodiment, a more rapid transition for prioritized events occurs since they are asynchronous and often happen when the system is "ready" for more work (idle.) [0040] In one embodiment, a user may increase the processing time for software- initiated events. For in - stance, an Excel chart and graph would likely compute and re-graph more quickly as a result of a user depress- ing a key on the keyboard. The occurrence of the user event causes the algorithm to immediately transition to higher levels of performance irrespective of the actual average percent CPU utilization. Thus in one embodi- ment, even during a software initiated processing task, such as the calculation for the Excel spreadsheet, the user mayincreasetheprocessingrate ofthoseequations by simply depressing a key. [0041] The computing system can be made aware of user events,such as keystrokes,mouse movement,joy- stick inputs, mouse clicks, human commands via micro- phone, etc. In one embodiment, the programming envi- ronment within which the processor is operating defines the user event. In this embodiment, the operating envi- ronment may define what event constitutes a user event and how to detect that event. [0042] In oneembodiment, the algorithmto controlthe performance state of the processor may reside in the operating software. In one embodiment, the algorithm to control the performance state of the processor may re- side in the  B asic  I nput  O utput System (BIOS). The BIOS can be an essential set of routines in a personal compu- ter, which is stored on a chip and provides an interface between the operating system and the hardware of the computer. In this embodiment, depending on the pro- gramming language and system architecture, the BIOS may be directly aware that a user event has occurred or may receive a notification, for example, from the operat- ing system that a user event has just occurred. In one embodiment, the algorithm to control the performance state of the processor may reside as an application pro- gram, an executable program module, or other similar program. In this embodiment, the application program, an executableprogram module, or other similar program may directly detect when a prioritized event such as a user event occurs or receive a notification from the op- erating system that the prioritized event occurred. [0043] In one embodiment, the threshold to trigger a transition in non-prioritized events may be a specific av- erage percent utilization of the CPU, such as 85%, tran- sitions based upon the idle vs. active ratio, or any other similar predefined threshold. [0044] In one embodiment, the algorithm controlling the performance state of the processor may be split into two discrete algorithms. A first algorithm to control tran- sitioning to a higher performance state. Likewise, a sec- ond algorithm to control transitioning to a lower perform- ance state. In one embodiment, the processor may per- form at the higher performance state for an extended sustainable period of time. In this embodiment, the high- est performance state in combination with the heat dis- sipationcapacityofthe systemissuch thateither extend- ed performance will not thermally damage any compo- nent withinthesystemor provisionsfor an overridemode are implemented.In one embodiment, theprocessormay performat the higher performancestate for a momentary ortransitoryperiodoftimedue tothermalconsiderations. [0045] Figure 3 illustrates a graph of various perform- ance states of one embodiment of an integrated circuit having multiple performance states including the per- formance state of operating at a higher state of perform- ance for a transient period of time. In one embodiment, the higher performance state of the processor may not be sustained for extended periods of time without poten- tially causing a failure in the system due to overheating a component. The graph illustrates the operational fre- quency of the processor over time. Three performance states are shown, such as at 500 MHz, the idle state of performance  302 , at 1000 MHz, the thermal maximum state of performance  304 , and at 2000 MHz, the actual highest state of performance  306  referred to as the peak virtual MHz. Multiple user events  308  occur during this timeperiodon the graph aswellasnon- user events  310 . [0046] Processing requests initiated by a non- user event  310 , such as application program, may only tran- sition the processor to the thermal higher state of per- formance  304 . The processor and other system compo- nents may operate at the thermal maximum state of per- formance  304  for sustained periodsoftimewithoutfailure dueto thermal considerations. A thermalguard band  312 exists between the actual higher state of performance 306  and the thermalmaximumstateof performance  304 . Prolonged operation at operating frequencies and volt- ages above the thermal maximum state of performance 304  could damagethermally sensitive componentssuch as integrated components. [0047] However, the occurrence or repetition of user events  308  occurs very slowly in respect to processing time. Many hundreds or thousands of non-user event processingrequests  310  maybe responded to by a proc- essor in the time frame it takes for a user to depress a first key and then a second key. Usually, a large relative lag time exists between a first user event  316  and a sec- ond user event  318 . The large time lag in between user events  308  generally allowsthe heat dissipation capacity of the computing system to remove the extra heat gen- erated by transitioning to the actual maximum state of performance  306  in response to the first user event  316 prior to the processor transitioning again to the actual maximum state of performance  306  in response to the second user event  318. [0048] However, some design safety precautions can be added.In oneembodiment, the transitionto the actual maximum state of performance  306  is for a transitory periodthat ensuresno component failures willoccur due 6