5  EP 1 499 943 B1 6  tion logic  134  includes circuitry that doubles, triples or otherwise multiplies the clock frequency by an integer or rational value before sending the clock signal onto inter- nal execution units of the processor  112.  For one em- bodiment, processor  112  itself includes circuitry thatdou- bles, triples or otherwise multiplies the clock frequency by an integer or rational value before sending the clock signal onto internalexecution unitsoftheprocessor  112. For example, the operating frequency of the processor 112  may be 250 megahertz ata lowstateof performance and even integer of eight times the initial frequency, or 2000 megahertz,at a higher state ofperformance.Inone embodiment, the clock couples to and controls the fre- quency at which the processor  112  operates. [0022] In one embodiment, processor  112  uses th e voltage supplied by voltage regulator logic  130  to power its operation. Voltage regulator logic  130  couples to a power supply  132  such asa battery ina batteryoperated computer system and generates the supply voltage that is supplied to processor  112 . In one embodiment, the voltage regulator couples to the processor in order to determine the voltage at which the processor operates. For example, the voltage regulator logic may supply a 1.8voltsvoltage leveland a higher3.3voltsvoltagelevel. [0023] In one embodiment, a power management al- gorithm  136 , in response to a particular predefined con- dition, such as a preset percent utilization of the proces- sor, signals the frequency regulation logic  134  to lower the operating frequency supplied to the processor  112 . Thus, the predefined condition lowers the frequency at which the processor  112  operates. Once the frequency is reduced, the frequency regulation logic  134  commu- nicates directlywiththevoltageregulator logic  130 , telling the voltage regulator logic  130  to lower the voltage sup- plied to the processor  112 . The voltage regulation logic 130  complies, and the processor  112  continues to oper- ate in this lower power performance state, reducing the power drain on the power supply  130 . [0024] In one embodiment,the power management al- gorithm  136,  in response to a particular prioritized event, such as detection of a user event, signals the frequency regulation logic  134  to raise the frequency to the higher operating frequency so that the processor can again op- erate at full speed. Before raising the frequency, howev- er, the frequency regulation logic  134  communicates di- rectly with the voltage regulation logic  130 , signaling the voltage regulation logic  130  to raise the supply voltage to the higher voltage level. The voltage regulation logic 134  responds tothisrequest and uponcompletion direct- ly communicates back to the frequency regulation logic 134  that the supply voltage has been raised. Upon re- ceiving this information from the voltage regulation logic 130 , the frequency regulation logic  134  then raises the frequency back to the higher value in order to allow the processor  112 to operate at the higher performanc state. In one embodiment, the power management algo- rithm  136  is split into two discreet algorithms. A first al- gorithm to decrease the transition of processor  112  from a higher stateofperformancetoalower state of perform- ance and a second algorithm to transition processor  112 from a lower state of performance to a higher state of performance. [0025] Note, various other configurations and imple- mentations in accordance with alternate embodiments of the present invention may exist. [0026] For example, in one embodiment, processor 112  may be a singleprocessor capableof operating with variable operating frequenciesand voltagelevels. Inone embodiment, processor  112  may be two or more proc- essors working inconjunction to respondto the process- ing load. In one embodiment, processor  112  may be a chipset having multiple performance modes. [0027] For example, thepower management algorithm 136  may be software based or hardware based such as arbitration logic may be shared between the processors or a combinationofsoftwarebased andhardware based. [0028] For example, in one embodiment" the power management algorithm  136  detects a user event. Upon detecting the user event, the power management algo- rithm  136  triggers the multiple performance state com- puter system  100  to transition to a higher performance state. The processor  112  has multiple states of perform- ance includinga first state ofperformance, asecond state of performance higher thanthe firststate ofperformance, and a third state of performance higher than the second state of performance. The algorithm directly transitions the processor  112  from the first state of performance to the third state of performance based upon detecting the user event. Note, the third state of performance may or may not be the maximum state of performance that the processor  112  can achieve. [0029] For example, in one embodiment, a prioritized event may bea directrequest for thehighest performance state directly or indirectly by initiating or simulating a be- nign user event by an application is aware of the power management algorithm  136 . [0030] Figure 2 illustrates a graph of various perform- ance states of one embodiment of an integrated circuit having multiple performance states. The top graph illus- trates the average percent CPU utilization  201  over time 203  for bothin response to theoccurrence of a prioritized event  207  and in response to the occurrence of non- prioritized events  209 . The bottom graph illustrates per- formance levelof the processor  205  over the same time- line for both inresponsetotheoccurrence ofa prioritized event  211  and in response to the occurrence of non- prioritized events  213 . The dotted line represents an ex- emplary average percent CPU utilization by non-priori- tized events  209  and the performance level transitions in responseto thosenon- prioritized events  213 . Thesolid line represents an exemplary average percent CPU uti- lization by a prioritized event  207  and the performance level transition in response to the prioritized event  211 . The algorithm to control the performance state of the processor may prioritize certain events such as user events, so that the occurrence of the prioritized event 4