3  EP 1 499 943 B1 4  [0009] figure1isa blockdiagram of anexemplarymul- tiple performance state computer system that may be used in conjunctionwithtransitioning an integrated circuit from a first performance state to the higher performance state upon detecting a user event; [0010] figure 2 illustrates a graph of various perform- ance states of one embodiment of an integrated circuit having multiple performance states; [0012] figure 4 illustrates a flow diagram of one em- bodiment of the algorithm to transition the state of per- formance of the integrated circuit. [0013] While the invention is subject to various modi- fications and alternative forms, specific embodiments thereofhavebeenshownbyway of example in thedraw- ings and will herein be described in detail. The invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to coverall modifications,equivalents,and alternativesfall- ing within the scope of the appended claims. [0011] figure 3 illustrates a graph of various perform- ance states of one embodiment of an integrated circuit having multiple performance states including the per- formance state of operating at a higher state of perform- ance for a transient period of time; and [0014] In the following description, numerous specific details are set forth, such as examples of specific data signals, named component blocks, levels of perform- ance, storage and operating locations of an algorithm, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be prac- ticed without these specific details. In other instances, well known components or methods have not been de- scribed in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Thus, thespecific details set forthare merelyexemplary. The specific details may be varied from and still be con- templated tobe withinthe scope ofthe appendedclaims. Theterm coupled is defined asmeaning connectedeither directly or indirectly. [0015] In general, a method, apparatus and system are described which allow a user event to trigger a direct transitionof anintegratedcircuit froma first performance state to a higher performance state. In one embodiment, thefirst performance statebeing a firstvoltage levelsup- plied to a processor and a first clock frequency of oper- ation for that processor or other similar integrated circuit in a computer system. In one embodiment, the higher performance state being a second higher voltage level supplied to the processor and a second higher clock fre- quency of operation for that processor. In one embodi- ment, the higher performance state adds a second proc- essor to manage the processing load. In one embodi- ment, lowering the clock frequency and/or voltage level of the processor reduces the power consumed by the [0021] In one embodiment, processor  112  uses the clock frequency supplied by frequency regulation logic 134  to coordinate the execution of instructions within the processor  112 . For one embodiment, frequency regula- [0020] Another device that may be coupledto bus  111 isa hard copy device  124 , which maybeusedfor printing instructions, data, or other information on a mediumsuch as paper, film, or similar types of media. Furthermore, a soundrecordingandplaybackdevice, suchasa speaker and/or microphone (not shown) may optionally be cou- pled to bus  111  for audio interfacing with computer sys- tem  100 . Another device thatmay be coupled to bus  111 isawired/ wirelesscommunicationcapability  125  tocom- munication to a phone. processor. In one embodiment, a power management algorithm controls the clock frequency and voltage sup- plied to the processor. [0016] Figure 1 is a block diagram of an exemplary multiple performance state computer system that may be used in conjunction with transitioning an integrated circuit from a first performance state to the higher per- formance state upon detecting a user event. In one em- bodiment, computer system  100  comprises a communi- cation mechanism or bus  111  for communicating infor- mation, and an integrated circuit component such as a processor  112  coupled with bus  111  for processing in- formation.Processor  112  may include a microprocessor, but is not limited to a microprocessor, such as a Pen- tium$^{™}$, PowerPC$^{™}$, Alpha$^{™}$, etc. [0017] Computer system  100  further comprises a ran- dom access memory (RAM), or other dynamic storage device  104  (referred to as main memory) coupled to bus 111  for storing information and instructions to be execut- ed by processor  112 . Main memory  104  also may be used for storing temporary variables or other intermedi- ate information during execution of instructions by proc- essor  112 . [0018] Computer system  100  also comprises a read only memory (ROM) and/or other static storage device 106  coupled to bus  111  for storing static information and instructionsfor processor  112,  anda massstorage mem- ory  107 , such as a magnetic disk or optical disk and its corresponding disk drive. Mass storage memory  107  is coupled to bus  111  for storing information and instruc- tions. [0019] Computer system  100  may further be coupled to adisplaydevice  121 , such asacathode ray tube(CRT) or liquid crystal display (LCD), coupled to bus  111  for displaying information to a computer user. An alphanu- meric input device (keyboard)  122 , including alphanu- meric and other keys, may also be coupled to bus  111 for communicating information and command selections to processor  112 . An additional userinputdeviceiscursor control device  123 ,suchasa mouse,trackball,trackpad, stylus, or cursor direction keys, coupled to bus  111  for communicating direction information and command se- lections to processor  112 , and for controlling cursor movement on a display device  112 . DETAILED DISCUSSION 3