7  EP 1 499 943 B1 8  202 may trigger instant access to a higher performance state in a multiple performance state integrated circuit, such as a processor. In an embodiment, the direct tran- sition isto thehighest performance state  204  inresponse to a prioritized event  202 . [0031] In one embodiment, in response to a trigger to transition to a higher state of performance initiated by a non-prioritized event, the algorithm to control the per- formance state of the processor utilizes real-time histor- ical data ofCPUutilization overa windowoftime (History window  208 ), such as the past one hundred microsec- onds, todetermineatransitionto, or from, the next higher performance state. In contrast, the algorithm to control the performance state of the processor immediately en- ables a higher performance state such as the highest state of performance  204,  for a defined period of time 206,  when a prioritized event  202  such as a user event, is triggered. The duration of the defined period of time 206 may include considerations such as whether that higher performance state would be sustainable or tran- sitory. [0032] As noted, the algorithm to control the perform- ance state of the processor impedes the transition to the next higher performance state for a time, in response to the occurrence of non-prioritized events such as soft- ware-initiated events. In one embodiment, the algorithm to control the performance state of the processor uses a requirement that the average percent utilization of the CPU  201  within the finite time period of the History Win- dow  208  be greater than a predetermined setting. When the average percent utilization of the CPU  201  within the time period of the History Window  208  is greater than a predetermined setting, such as a setting of 85% usage, then the algorithm to controlthe performance state ofthe processor incrementallytransitions the processor tofast- er states of performance. [0033] For example, after exceeding the tr amount setfor the average percent utilizationofthe CPU, the algorithm may transition the processor from a mini- mum state of performance such as a sleep state of per- formance  210 to a next higher state, the idle state performance  212 . A first brief time period  214  passes and the algorithm checks the CPU utilization  201  within the time period of the History Window  206 . The history window  208  representing a recordationof themostrecent finite spanof time alongthe timeline, suchasthe lastone hundred microseconds, reflects a higher average per- cent CPU utilization  201 . The average percent CPU uti- lization  201  will have changed because the demand for the greater CPU utilization  201  has been in the exami- nation time frame of the history window  206  for a greater percentage of the time and because the CPU itself has been performing at a higher processing or performance state for a portion of the examination time frame of the history window  206 . [0034] Note, inoneembodiment, thesleepstate isthe lowest state of performance, the idle state is the next higherstateofperformance,the active state isthe second from the highest state of performance, and the higher state ofperformance isthe highest stateof performance. Four states of performance are described in this exam- ple. However, two or more states of performance may exist in any embodiment. [0035] When the preset average percent utilization of the CPU still exceeds the preset threshold such as 95%, then thealgorithm transitions the processor from the idle state of performance  212  to next higher state, such as the active state of performance  216.  A second brief time period  218  passes and the algorithm checks the CPU utilization within the time period of the History Window 206 . [0036] However, if the preset average percent utiliza- tion of the CPU still exceeds the trigger threshold, then the algorithmmaytransitionthe processor fromtheactive state of performance  216  to next higher state, such as the highest state of performance  204.  Thus, in this ex- ample,a third timeperiod  220  equalto allof thetransition time periods elapses beforethe processor transitionsinto the highest performance state  204 . The algorithm may use this incremental increase in processing power over time to balancea demandfor increased performanceand an attempt to reduce the power drain on the power sup- ply. [0037] Note, even if the demand for CPU utilization increases to one hundred percent instantly, the trigger threshold such as 95% average percent CPU utilization may not be exceeded until the average over the entire span of the finite time period in the History Window  206 equals or exceeds 95%. Thus, a time weighted delay occurs before the algorithm triggers a transition of the processor to a higher state. [0038] In contrast, when a prioritized event  202  such as a user event, is triggered, then the algorithm immedi- ately transitions the processor to a higher state of per- formance such as active state of performance  216 or highest state of performance  204 . The detection of the prioritized event  202  forces the algorithm to immediate transition to a higher performance state bypassing the levelof performance immediatelyhigher thanthecurrent level of performance. In an embodiment, how many lev- els of performance the algorithm bypasses over is de- pendant on conditions such as thermal considerations and available battery power. In an embodiment, if the processor only has two levels of performance, than the algorithm transitions the processor to the highest level of performance. Note, for this embodiment, the compu- tational overhead of the % CPU utilization determination may be averted. [0039] When the processor transitions to the higher state of performance in response to the priority event, theactual average percent CPUutilization may decrease because the processing load may not have increased butthe performance capacityof the processor increased. For example, the processor may be operating at 50% CPUutilization  201  prior to the occurrence ofaprioritized event  202 . The algorithm may transition the processor 5