DLS: Directoryless Shared Last-level Cache
  Directory-based protocols have been the de facto solution for maintaining cache coherence in shared-memory parallel systems comprising multi/many cores, where each store instruction is eagerly made globally visible by invalidating the private cache (PC) backups of other cores. Consequently, the directory not only consumes large chip area, but also incurs considerable energy consumption and performance degradation, due to the large number of Invalidation/Ack messages transferred in the interconnection network and resulting network congestion. In this paper, we reveal the interesting fact that the directory is actually an unnecessary luxury for practical parallel systems. Because of widely deployed software/hardware techniques involving instruction reordering, most (if not all) parallel systems work under the weak consistency model, where a remote store instruction is allowed to be invisible to a core before the next synchronization of the core, instead of being made visible eagerly by invalidating PC backups of other cores. Based on this key observation, we propose a lightweight novel scheme called {\em DLS (DirectoryLess Shared last-level cache)}, which completely removes the directory and Invalidation/Ack messages, and efficiently maintains cache coherence using a novel {\em self-suspicion + speculative execution} mechanism. Experimental results over SPLASH-2 benchmarks show that on a 16-core processor, DLS not only completely removes the chip area cost of the directory, but also improves processor performance by 11.08%, reduces overall network traffic by 28.83%, and reduces energy consumption of the network by 15.65% on average (compared with traditional MESI protocol with full directory). Moreover, DLS does not involve any modification to programming languages and compilers, and hence is seamlessly compatible with legacy codes. 
Daofu Liu, Yunji Chen, Qi Guo, Tianshi Chen, Ling Li, Qunfeng Dong,   Weiwu Hu
cs.AR