Accelerating Algorithms using a Dataflow Graph in a Reconfigurable   System
  In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper. 
Jorge Luiz e Silva and Joelmir Jose Lopes and Bruno de Abreu Silva and   Antonio Carlos Fernandes da Silva
cs.AR