Interface trap density metrology from sub-threshold transport in highly   scaled undoped Si n-FinFETs
  Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage. 
Abhijeet Paul, Giuseppe C. Tettamanzi, Sunhee Lee, Saumitra Mehrotra,   Nadine Colleart, Serge Biesemans, Sven Rogge and Ger...
cond-mat.mes-hall cond-mat.mtrl-sci