Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic   Devices
  We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme. 
Jayita Das, Syed M. Alam, Srinath Rajaram, Sanjukta Bhanja
cs.ET cond-mat.mes-hall