Memory Aware High-Level Synthesis for Embedded Systems
  We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Finally, we show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area. 
Gwenol\'e Corre (LESTER), Eric Senn (LESTER), Nathalie Julien   (LESTER), Eric Martin (LESTER)