Development of SyReC based expandable reversible logic circuits
  Reversible computing is gaining high interest from researchers due to its various promises. One of the prominent advantages perceived from reversible logic is that of reduced power dissipation with many reversible gates at hand, designing a reversible circuit (combinational) has received due attention and achievement. A proposed language for description of reversible circuit, namely SyReC, is also in place. What remain are the software tools which would help in reversible circuit synthesis through simulation. Beginning with the smallest reversible circuit realizations the SyReC statements and expressions, we employ a hierarchal approach to develop a complete reversible circuit, entirely from its SyReC code. We implement this as a software tool. The tool allows a user to expand a reversible circuit of choice in terms of bit width of its inputs. The background approach of expansion of a reversible circuit has also been proposed as a part of this dissertation. Also, a user can use the tool to observe the effect of expansion on incurred costs, in terms of increase in number of lines, number of gates and quantum cost. The importance of observing the change in costs with respect to scale of expansion is important not only from analysis point of view, but also because the cost depends on the approach used for expansion. This dissertation also proposes a reversible circuit design for elevator controller (combinational) and the related costs. The aim is to emphasize use of the proposed approach is designing customized circuits. 
Vandana Maheshwari
cs.AR