Formal and Informal Methods for Multi-Core Design Space Exploration
  We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain. 
Jean-Francois Kempf (VERIMAG), Olivier Lebeltel (VERIMAG), Oded Maler   (VERIMAG)
cs.SE cs.PF