Multiplierless Approximate 4-point DCT VLSI Architectures for Transform   Block Coding
  Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption. 
F. M. Bayer, R. J. Cintra, A. Madanayake, U. S. Potluri
cs.AR cs.MM cs.NA