Thermo Activated Hysteresis on High Quality Graphene/h-BN Devices
  We report on gate hysteresis in resistance on high quality graphene/h-BN devices. We observe a thermal activated hysteretic behavior in resistance as a function of the applied gate voltage at temperatures above 375K. In order to investigate the origin of the hysteretic phenomenon, we design heterostructures involving graphene/h-BN devices with different underlying substrates such as: SiO2/Si and graphite; where heavily doped silicon and graphite are used as a back gate electrodes, respectively. The gate hysteretic behavior of the resistance shows to be present only in devices with an h-BN/SiO2 interface and is dependent on the orientation of the applied gate electric field and sweep rate. Finally, we suggest a phenomenological model, which captures all of our findings based on charges trapped at the h-BN/SiO2. Certainly, such hysteretic behavior in graphene resistance represents a technological problem for the application of graphene devices at high temperatures, but conversely, it can open new routes for applications on digital electronics and graphene memory devices. 
A. R. Cadore, E. Mania, K. Watanabe, T. Taniguchi, R. G. Lacerda, L.   C. Campos
cond-mat.mes-hall