Reliability-Aware Overlay Architectures for FPGAs: Features and Design   Challenges
  The FPGA overlay architectures have been mainly proposed to improve design productivity, circuit portability and system debugging. In this paper, we address the use of overlay architectures for building fault tolerant SRAM-based FPGA systems and discuss the main features and design challenges of a reliability-aware overlay architecture. 
Mihalis Psarakis
cs.AR