Improving FPGA resilience through Partial Dynamic Reconfiguration
  This paper explores advances in reconfiguration properties of SRAM-based FPGAs, namely Partial Dynamic Reconfiguration, to improve the resilience of critical systems that take advantage of this technology. Commercial of-the-shelf state-of-the-art FPGA devices use SRAM cells for the configuration memory, which allow an increase in both performance and capacity. The fast access times and unlimited number of writes of this technology, reduces reconfiguration delays and extends the device lifetime but, at the same time, makes them more sensitive to radiation effects, in the form of Single Event Upsets. To overcome this limitation, manufacturers have proposed a few fault tolerant approaches, which rely on space/time redundancy and configuration memory content recovery - scrubbing. In this paper, we first present radiation effects on these devices and investigate the applicability of the most commonly used fault tolerant approaches, and then propose an approach to improve FPGA resilience, through the use of a less intrusive failure prediction scrubbing. It is expected that this approach relieves the system designer from dependability concerns and reduces both time intrusiveness and overall power consumption. 
Jose Luis Nunes
cs.DC