Algorithmic Aspects of VLSI
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{'SignBlockName': 'John R. Lehmann', 'PO_EMAI': None, 'PO_PHON': None}
This research studies a number of algorithmic issues related to the             design of VLSI chips and wafers.  The foremost interest is the problem          of the efficient design of fault-tolerant arrays of processors.  Next           in priority is the problem of how to render feasible the exhaustive             test approach to VLSI self-test.  A third continuing area of concern is         multilayer circuit realizations, where the attention is shifting from           abstract layout-theoretic issues to CAD-algorithmic ones.  A new area           of interest includes algorithmic (in contrast to systems-oriented)              aspects of the "silicon compilation" problem.  All of these topics              encompass problems ranging from abstract mathematical questions to              concrete engineering issues.  The intent is to tackle the problems at           several points along this abstract-to-concrete spectrum.
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{'Code': '1457', 'Text': 'COMPUTER ENGINEERING (OTHER)'}
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