Parallel Algorithms for VLSI Circuit Extraction on          Multiprocessors
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{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
The focus of Dr. Banerjee's work is VLSI CAD tools which run on a               class of message-passing architectures, such as hypercubes.  In                 this research he will investigate algorithms for tools which                    perform the task of circuit extraction from VLSI mask layouts.                  The technical approach is to flatten the hierarchical description               into a mask description consisting of rectangles, and perform the               extraction at this level.  The new multiprocessor algorithms will               be used for speedup and accurate, fast-circuit extraction.  The                 algorithms will use region queries in parallel on a data                        structure distributed over the parallel processor.  It is                       anticipated that this procedure will avoid the boundary effect                  problems that may arise when splitting a VLSI layout area into                  regions.
{'FirstName': 'Prithviraj', 'LastName': 'Banerjee', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Prithviraj Banerjee', 'EmailAddress': 'prith@uic.edu', 'PI_PHON': '3129962400', 'NSF_ID': '000306284', 'StartDate': '01/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Illinois at Urbana-Champaign', 'CityName': 'URBANA', 'ZipCode': '618013620', 'PhoneNumber': '2173332187', 'StreetAddress': '506 S WRIGHT ST', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Illinois', 'StateCode': 'IL', 'CONGRESSDISTRICT': '13', 'CONGRESS_DISTRICT_ORG': 'IL13', 'ORG_UEI_NUM': 'Y8CWNJRCNN91', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF ILLINOIS', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
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