Simplified Implementation of Digital Signal Processors Basedon Delta Modulation Encoding
{'Code': '05010800', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'John Cozzens', 'PO_EMAI': None, 'PO_PHON': None}
This research continues an investigation in the area of new                     unconventional structures for digital signal processing.  Instead of a          conventional analog-to-digital converter, which produces a sampled              signal output, the present research considers using the output of a             delta modulator.  While the sample rate must be increased considerably,         digital filtering can then be performed without any multiplications,            which has the potential to simplify the implementation in VLSI hardware         and also lower chip-area requirements.                                                                                                                          Previous work of the investigators has been concerned with FIR                  structures. This work is concerned with IIR filters and adaptive                filters which are designed based on the new approach. The investigators         are exploring the relation of their work to the sigma-delta modulator           studied in A/D conversion and the variety of processor implementations          that can result as the decimation rate is varied in that approach.              This grant continues on-going research concerned with novel approaches          to digital signal processing.  The digital filters that are the concern         of this research have wide application in military, consumer, and               medical equipment.  The filters are both fixed and adaptive and are             generally used to separate out desired signals from undesired signals           and noise.  This research is concerned with the simplifications of the          algorithmic requirements on the VLSI hardware that are possible when a          novel high-speed analog sampling is performed.
{'FirstName': 'F.', 'LastName': 'Hill', 'PI_MID_INIT': 'S', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'F. S Hill', 'EmailAddress': None, 'NSF_ID': '000091770', 'StartDate': '10/15/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Massachusetts Amherst', 'CityName': 'AMHERST', 'ZipCode': '010039252', 'PhoneNumber': '4135450698', 'StreetAddress': '101 COMMONWEALTH AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Massachusetts', 'StateCode': 'MA', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'MA02', 'ORG_UEI_NUM': 'VGJHK59NMPK9', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF MASSACHUSETTS', 'ORG_PRNT_UEI_NUM': 'VGJHK59NMPK9'}
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[{'Code': '4720', 'Text': 'SIGNAL PROCESSING SYS PROGRAM'}, {'Code': '9145', 'Text': 'SPECIAL PROGRAMS-RESERVE'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1986&All=true', 'xml': '8613299.xml'}