An Expert System for Layout Generation
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
The research is on a prototype expert system for layout                         generation in a hierarchial VLSI system.  It applies a                          combination of rule-based and algorithmic-based techniques to a                 new layout style. Initial tests on a set of simple benchmarks                   have demonstrated the superiority of this expert system over                    various standard cell systems and its                                           competitiveness with the human designer in terms of layout                      quality.  Further research seeks to understand the full potential               of this idea and develop a new design methodology that may                      replace the standard-cell design method.                                                                                                                        Specific research is in four areas:  (1) adapt the prototype                    system so that it can use user-defined sizes of transistors and                 gates in the input description; (2) revise the strategy of                      knowledge representation so as to permit rules to be divided into               smaller sets, and investigate the types of rules in a set as well               as the granularity of the sets and the order in which they are                  applied; (3) study the problem of translation of symbolic to                    geometric representation with local restructuring using knowledge               of the circuit functionality and the global floor plan; and (4)                 collect an extensive set of benchmarks for comparing layouts                    generated by different systems, and develop methods of comparison               of layout quality.
{'FirstName': 'Daniel', 'LastName': 'Gajski', 'PI_MID_INIT': 'D', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Daniel D Gajski', 'EmailAddress': 'gajski@uci.edu', 'NSF_ID': '000208010', 'StartDate': '01/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of California-Irvine', 'CityName': 'IRVINE', 'ZipCode': '926970001', 'PhoneNumber': '9498247295', 'StreetAddress': '160 ALDRICH HALL', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '47', 'CONGRESS_DISTRICT_ORG': 'CA47', 'ORG_UEI_NUM': 'MJC5FCYQTPE6', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF CALIFORNIA IRVINE', 'ORG_PRNT_UEI_NUM': 'MJC5FCYQTPE6'}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '471000', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8711025.xml'}