Vector Processors for Systolic Arrays
{'Code': '15030000', 'Directorate': {'Abbreviation': 'TIP', 'LongName': 'Dir for Tech, Innovation, & Partnerships'}, 'Division': {'Abbreviation': 'TI', 'LongName': 'Translational Impacts'}}
{'SignBlockName': 'Ritchie B. Coryell', 'PO_EMAI': None, 'PO_PHON': None}
The digital signal and image processing industry continues to grow.             However, many compute-bound, high-end, real-time needs are not                  currently being met.  Application areas typifying these requirements            are communications, radar/sonar, speech and scene analysis, computer            vision and graphics.  A new and powerful class of digital processor             architectures is required to meet this need.  This research is on a new         digital processor design that has potential for significant increases           in speed, area-speed and cost-performance measures.  It can provide             multi-megahertz fixed and floating point operation on one VLSI chip.            Its innovative bit-serial interprocessor I/O structure makes it a               candidate for fine-grain systolic array applications.  The design goal          is a system which achieves ten to one hundred MFLOP per chip                    computational bandwidth in a small, low cost package.  This is in the           class of desktop supercomputers.  Such a machine could be used as an            attached co-processor in general applications or embedded into signal           and imaging systems in application specific environments.                       Reviewers gave this scores of 15, 15 and 18, which are quite high               relative to all the scores.  The three reviewers saw this as having al          well-developed research plan, with high probability of good results             leading to Phase II work.  They said it is an important problem with            substantial payoff.  Solutions will contribute to the design of future          instruments that depend on rapid processing of large arrays of numbers.         The qualifications of the personnel are excellent.
{'FirstName': 'Michael', 'LastName': 'Griffin', 'PI_MID_INIT': 'F', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Michael F Griffin', 'EmailAddress': None, 'PI_PHON': None, 'NSF_ID': '000279514', 'StartDate': '01/01/1989', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Peregrine Engineering', 'CityName': 'Gainesville', 'ZipCode': '326052165', 'PhoneNumber': '9043712567', 'StreetAddress': '3424 NW 31st Street', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Florida', 'StateCode': 'FL', 'CONGRESSDISTRICT': '03', 'CONGRESS_DISTRICT_ORG': 'FL03', 'ORG_UEI_NUM': None, 'ORG_LGL_BUS_NAME': None, 'ORG_PRNT_UEI_NUM': None}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '5371', 'Text': 'SBIR Phase I'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8861368.xml'}