Generalized Data Compression Techniques for Testable        Design of Very Large Scale Integrated Circuits
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{'SignBlockName': 'Ritchie B. Coryell', 'PO_EMAI': None, 'PO_PHON': None}
With the increase in our dependence on computers in all phases of our           lives, it is becoming imperative that, as far as possible, the                  computers be fault-tolerant, i.e. be capable of performing in the               presence of failures.  One critical aspect of fault-tolerant computing          is the necessity to design testable VLSI circuits.                                                                                                              In this research project, a new technique for Built-in-test (BIT) of            VLSI circuits is presented.  The technique is based on the generalized          data compression concept and assumes underlying Built-In-Logic Block-           Observability (BILBO) and Level-Sensitive-Scan-Design (LSSD)                    structures.  The technique addresses two main aspects of the testable           design of VLSI, namely,                                                                                                                                         i)  Design of reduced size test patterns through a new data compression         algorithm generated using a fault information data base.                                                                                                        ii)  Circuit modification or augmentation for testability i.e. by               proper selection of suitable finite state models, implementations as            programmable arrays with and without observable outputs are realized.           Then necessary heuristics for testing are generated.                                                                                                            This technique may be used for BIT test of certain crucial parts of a           computer, such as a "control unit", for ensuring system reliability and         for reducing the overall testing time and cost.
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{'Name': 'Compression Telecommunications Corporation', 'CityName': 'Germantown', 'ZipCode': '208741202', 'PhoneNumber': '3014289405', 'StreetAddress': '19540 Amaranth Dr', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Maryland', 'StateCode': 'MD', 'CONGRESSDISTRICT': '06', 'CONGRESS_DISTRICT_ORG': 'MD06', 'ORG_UEI_NUM': None, 'ORG_LGL_BUS_NAME': None, 'ORG_PRNT_UEI_NUM': None}
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{'Code': '5371', 'Text': 'SBIR Phase I'}
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