Parallel Architecture: Design, Validation, Implementation
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Yechezkel Zalcstein', 'PO_EMAI': 'zzalcste@nsf.gov', 'PO_PHON': '7032920000'}
This project is a program of research on theoretical aspects of the             design cycle for a special genre parallel architectures, namely,                multipurpose arrays of identical processing elements (arrays, for               short).  The first phase of the program will concern itself with issues         concerning the design of arrays, concentrating on questions concerning          the relative computational efficiency gained by incorporating a variety         of structural features into the design.  As but one example, what are           the relative merits of point to point communication vs. communication           via shared memories vs. communication via (reconfigurable) busses?  The         main vehicle for this phase will be studies of the intersimulatability          of architectures.  The second phase of the program will concentrate on          the problem of validating a proposed multipurpose architecture by               demonstrating its ability to handle a variety of classes of                     computational tasks efficiently.  The main vehicle for this will be an          enhanced version of the logical mapping problem for parallel                    architectures.  The final phase of the program will be concerned with           the physical implementation of the proposed architecture, focusing on           issues such as fault-tolerance and efficient implementability in                physical space.  One major tool in this phase will be the new notion of         the physical mapping problem for parallel architectures. Throughout,            our measures of efficiency will include delay, resource utilization,            and load balancing; and, we shall consider a variety of modes of                parallel computation, viewing SIMD and MIMD as the extremes in the              spectrum of modes.
{'FirstName': 'Arnold', 'LastName': 'Rosenberg', 'PI_MID_INIT': 'L', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Arnold L Rosenberg', 'EmailAddress': 'rsnbrg@cs.umass.edu', 'NSF_ID': '000097177', 'StartDate': '11/15/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Massachusetts Amherst', 'CityName': 'AMHERST', 'ZipCode': '010039252', 'PhoneNumber': '4135450698', 'StreetAddress': '101 COMMONWEALTH AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Massachusetts', 'StateCode': 'MA', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'MA02', 'ORG_UEI_NUM': 'VGJHK59NMPK9', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF MASSACHUSETTS', 'ORG_PRNT_UEI_NUM': 'VGJHK59NMPK9'}
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[{'Code': '2860', 'Text': 'THEORY OF COMPUTING'}, {'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}, {'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8812567.xml'}