Performance Evaluation of Parallel Logic Programming        Paradigms (Computer and Information Science)
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A shared memory multiprocessor testbed will be built for                measuring parallel logic programming language architectures.  The               purpose of developing the testbed is to compare several parallel                implementations of logic programming languages to determine which               paradigm offers greater cost-effective performance.  An equally                 important goal is the determination of the memory characteristics               of, and memory designs suitable for those languages.                                    The testbed, enabling empirical measurement of benchmark                performance, will be composed of architecture emulators and                     memory simulators running on a host multiprocessor.  Processor                  performance is estimated as required shared memory bandwidth                    because high speed processors are ultimately limited by memory                  bandwidth and architectures that require less bandwidth have                    greater potential for high performance.  Memory performance                     statistics to be collected include local cache miss ratio,                      traffic ratio, broadcast traffic (necessary to retain consistency               between caches).  This methodology is most suited for ongoing                   processor design efforts, like the PIM project at ICOT, because                 experimental memory designs can be quickly described, tested and                results compared with other models.                                                     This project is a collaborative effort with the Japanese                Institute for New Generation Computer Technology (ICOT) and                     funded under the NSF/ICOT Visitors Program.
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[{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}, {'Code': '6840', 'Text': 'ROBOTICS'}]
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