International Workshop on Defect and Fault Tolerance in     VLSI Systems; October 6-7, 1988; Springfield, Massachusetts
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
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The workshop addresses problems on defect tolerance and fault tolerance         in complex VLSI (Very Large Scale Integration) and WSI (Wafer Scale             Integration) systems.  Its objective is to bring together researchers           and designers in the above problem areas with developers of appropriate         computer-aided design (CAD) tools and innovative packaging techniques.          Its scope includes (a) defect and fault tolerant computer                       architectures; (b) defect and fault tolerant memories; (c) techniques           for yield enhancements; (d) fault models and defect models; (e)                 statistical modeling of defects and yield; (f) repair and restructuring         techniques; (g) packaging technologies for WSI and 3-D VLSI circuits;           (h) high density hybrid circuits; (i) CAD tools; and (j) experimental           systems.                                                                                                                                                        The research will bring together researchers and practitioners in both          industry and academia in the U.S. and abroad to discuss problems on             fabrication defects, yield models, and chip designs for yield                   enhancement.  It will foster better interactions between industry and           academia in understanding fabrication defects and developing defect             tolerant and fault tolerant techniques and systems.                                                                                                             The program committee consists of distinguished researchers in academia         and industry.  The workshop organizers have done extensive research in          this area and are well respected in the problem areas addressed by the          workshop.                                                                       The grant funded by the National Science Foundation will be used to             support travel for a keynote speaker and the printing cost of                   proceedings for conference attendees.  Without the support from NSF,            the cost of registration will be exceedingly high for the limited               number of workshop attendees.  Support is, therefore, highly                    recommended.
[{'FirstName': 'Adit', 'LastName': 'Singh', 'PI_MID_INIT': 'D', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Adit D Singh', 'EmailAddress': 'adsingh@eng.auburn.edu', 'NSF_ID': '000239664', 'StartDate': '07/01/1988', 'EndDate': None, 'RoleCode': 'Co-Principal Investigator'}, {'FirstName': 'Israel', 'LastName': 'Koren', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Israel Koren', 'EmailAddress': 'koren@ecs.umass.edu', 'NSF_ID': '000471910', 'StartDate': '07/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}]
{'Name': 'University of Massachusetts Amherst', 'CityName': 'AMHERST', 'ZipCode': '010039252', 'PhoneNumber': '4135450698', 'StreetAddress': '101 COMMONWEALTH AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Massachusetts', 'StateCode': 'MA', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'MA02', 'ORG_UEI_NUM': 'VGJHK59NMPK9', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF MASSACHUSETTS', 'ORG_PRNT_UEI_NUM': 'VGJHK59NMPK9'}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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