Design and Analysis of Fault-Tolerant Programmable Logic    Arrays
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
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To attain significant improvements in yield with greater chip density,          many semiconductor manufacturers have successfully employed redundancy          techniques in the memory chip design, such as 64K DRAMs, 256K DRAMs,            etc. Recently, due to the regular structure, Programmable Logic Arrays          (PLAs) have become increasingly common for implementing Boolean logic           functions in VLSI.  This research is investigating an alternative PLA           design with redundancy that will exploit the repairability of the               partially defective chips in order to enhance the chip yield.  The              objectives of the research are to design and repair a fault-tolerant PLA        and apply this design concept to any other array logic, such as                 programmable array logic (PAL), as well as Wafer-Scale Integration (WSI)        design. The use of PLA structure, particularly in the control portion of        a VLSI microprocessor, improves design productivity, shortens design            time, simplifies the physical design of the chip, and facilitates the           implementation of engineering changes.  Semiconductor device                    manufacturers, continuously strive to increase chip complexity, reduce          the speed-power product, increase reliability and produce useful and            cost-effective devices.  However, increasing the chip complexity would          enhance the probability of having defective chips and then increase the         cost.  The proposed research will provide the new design and repair             scheme to enhance the chip yields.
{'FirstName': 'Chin-Long', 'LastName': 'Wey', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Chin-Long Wey', 'EmailAddress': 'wey@egr.msu.edu', 'NSF_ID': '000400312', 'StartDate': '06/15/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Michigan State University', 'CityName': 'EAST LANSING', 'ZipCode': '488242600', 'PhoneNumber': '5173555040', 'StreetAddress': '426 AUDITORIUM RD RM 2', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Michigan', 'StateCode': 'MI', 'CONGRESSDISTRICT': '07', 'CONGRESS_DISTRICT_ORG': 'MI07', 'ORG_UEI_NUM': 'R28EKN92ZTZ9', 'ORG_LGL_BUS_NAME': 'MICHIGAN STATE UNIVERSITY', 'ORG_PRNT_UEI_NUM': 'VJKZC4D1JN36'}
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[{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}, {'Code': '9120', 'Text': 'CROSS-DIRECTORATE PROGRAMS'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8700880.xml'}