High-Performance Multiple-Bus Computer Architectures
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
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This research addresses the major architectural and technological               trade-offs inherent in multiple-bus computer systems.  The focus                will be on two main issues:  (1) analysis of the basic                          architectural features of multiple-bus systems; and (2)                         development of new performance models for such systems.                         Technology-dependent analytical models that account for the                     loading, crosspoint control, and access arbitration in shared-                  memory architectures are being developed.  The recently                         introduced crosspoint cache will be further explored.  Together                 with an address-trace generation, parameters are provided in the                development and evaluation of a new semi-Markov bus performance                 model.  Efficient reconfiguration strategies for systems with bus               failures are also integrated into the performance models.
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{'Name': 'Regents of the University of Michigan - Ann Arbor', 'CityName': 'ANN ARBOR', 'ZipCode': '481091079', 'PhoneNumber': '7347636438', 'StreetAddress': '1109 GEDDES AVE, SUITE 3300', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Michigan', 'StateCode': 'MI', 'CONGRESSDISTRICT': '06', 'CONGRESS_DISTRICT_ORG': 'MI06', 'ORG_UEI_NUM': 'GNJ7BBP73WE9', 'ORG_LGL_BUS_NAME': 'REGENTS OF THE UNIVERSITY OF MICHIGAN', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '471500', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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