Meta-functions for Synthesizing Correct Arithmetic Hardware
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'John R. Lehmann', 'PO_EMAI': None, 'PO_PHON': None}
The objective of this project is to develop hardware generation                 functions that synthesize hardware correctly.  The existence of such            functions would result in a significant savings in design time because          the validation effort occurs only once.  Only the generating function           needs to be proven correct.  The candidate techniques which will be             extended to produce practical designs are:  (1) the use of proven               correct recursive functions to generate Boolean logic; (2) compiling,           specifying, and verifying timing and control hardware from                      specifications written using temporal logic or the notation of Hoare's          Communicating Sequential Processes (CSP); and (3) the application of            equivalence transformations to rewrite high-level specifications into           hardware generation functions which produce practical and correct               arithmetic hardware.  Candidate arithmetic functions include                    transcendental functions that are calculated based on the algorithm used        by the coordinate rotation digital computer (CORDIC).                           Hardware meta-functions are one class of tool to manage the complexity          of VLSI design.  The large gate counts associated with VLSI circuit             technology makes unrealistic the hope that correct detailed                     interconnection lists and block diagrams can be synthesized manually.                                                                                           Correct and automated synthesis methods like hardware meta-functions            offer the attractive possibility of creating correct designs from the           start. Thus, the growing impracticality of validating large designs             using simulation is avoided.
{'FirstName': 'Shiu-Kai', 'LastName': 'Chin', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Shiu-Kai Chin', 'EmailAddress': 'skchin@syr.edu', 'NSF_ID': '000171402', 'StartDate': '07/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Syracuse University', 'CityName': 'SYRACUSE', 'ZipCode': '13244', 'PhoneNumber': '3154432807', 'StreetAddress': '900 S CROUSE AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'New York', 'StateCode': 'NY', 'CONGRESSDISTRICT': '22', 'CONGRESS_DISTRICT_ORG': 'NY22', 'ORG_UEI_NUM': 'C4BXLBC11LC6', 'ORG_LGL_BUS_NAME': 'SYRACUSE UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '471500', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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