Propagation Delays in the Bilevel and Trilevel Multilayer   High Density Interconnections on the GaAs Based VHSIC
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'John R. Lehmann', 'PO_EMAI': None, 'PO_PHON': None}
There is an increasing demand for circuits with higher speeds and higher        component densities.  This requires millions of closely spaced                  interconnection lines that integrate the components on a chip.                  Parasitic capacitances associated with the interconnections in such high        density environments have become the primary factors in the evolution of        the VHSIC technology.  Particularly for the development of the ASIC's           (application specific integrated circuits), it is important to know the         propagation delays expected in an IC (integrated circuit) before its            fabrication is undertaken.  Objectives of the proposed research are:            (a) development of reliable models for the parasitic capacitances               associated with the multilevel and multilayer interconnection in the            high-density environments, suitable for the GaAs-based VLSI circuits;           (b) development of accurate models for the determination of the                 propagation delays in the multilevel and multilayer interconnections on         the GaAs-based very high speed integrated circuits; (c) study of the            crosstalk in the interconnections on the GaAs-based very high speed             integrated circuits; and (d) fabrication of the interconnection lines on        the GaAs substrate and experimental verification of the dependence of           the propagation delays on the interconnect dimensions, interconnect             material resistivity and other geometrical factors.                             This research is expected to provide a better understanding of the              interactions between interconnection lines on VLSI chips as the                 dimensions decrease and the density of the interconnections on a chip           increase. This is very important to the continued development of VLSI           technology.
{'FirstName': 'Ashok', 'LastName': 'Goel', 'PI_MID_INIT': 'K', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Ashok K Goel', 'EmailAddress': 'goel@mtu.edu', 'NSF_ID': '000175715', 'StartDate': '09/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Michigan Technological University', 'CityName': 'HOUGHTON', 'ZipCode': '499311200', 'PhoneNumber': '9064871885', 'StreetAddress': '1400 TOWNSEND DR', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Michigan', 'StateCode': 'MI', 'CONGRESSDISTRICT': '01', 'CONGRESS_DISTRICT_ORG': 'MI01', 'ORG_UEI_NUM': 'GKMSN3DA6P91', 'ORG_LGL_BUS_NAME': 'MICHIGAN TECHNOLOGICAL UNIVERSITY', 'ORG_PRNT_UEI_NUM': 'GKMSN3DA6P91'}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
[{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}, {'Code': '9120', 'Text': 'CROSS-DIRECTORATE PROGRAMS'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8710757.xml'}