Research Initiation:  Reconfigurable Complex DSP Systolic   Arrays
{'Code': '05010800', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'John R. Lehmann', 'PO_EMAI': None, 'PO_PHON': None}
The VLSI realization of Digital Signal Processing (DSP)                         algorithms provides both new opportunities and design challenges.               This work attempts to maximize the speed and reliability of such                array structures for DSP by employing residue number systems                    (RNS) and a new fault tolerant mechanism.  Several working                      algorithm specific integrated circuits (ASIC's) are being                       generated in both NMOS and CMOS technologies.
{'FirstName': 'Magdy', 'LastName': 'Bayoumi', 'PI_MID_INIT': 'A', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Magdy A Bayoumi', 'EmailAddress': 'mab@cacs.louisiana.edu', 'NSF_ID': '000396987', 'StartDate': '06/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Louisiana at Lafayette', 'CityName': 'LAFAYETTE', 'ZipCode': '705032014', 'PhoneNumber': '3374825811', 'StreetAddress': '104 E UNIVERSITY AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Louisiana', 'StateCode': 'LA', 'CONGRESSDISTRICT': '03', 'CONGRESS_DISTRICT_ORG': 'LA03', 'ORG_UEI_NUM': 'C169K7T4QZ96', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF LOUISIANA AT LAFAYETTE', 'ORG_PRNT_UEI_NUM': 'C169K7T4QZ96'}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '472500', 'Text': 'EXPERIMENTAL SYSTEMS/CADRE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8809811.xml'}