Scheduling and Code Generation for Pipelined Architectures
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Yechezkel Zalcstein'}
The primary aim of the proposed research is the development of                  static scheduling techniques for multiple, multifunctional and                  reconfigurable pipelined operational units.  Such units are the                 key elements of high performance computing engines.  A voracious                pipeline scheduling algorithm driven by the earliest completion                 time of tasks is proposed.  The method provides good schedules at               the basic block level.  The intention is to extend it by                        researching and implementing the following concepts:  static                    scheduling technique(s) for pipelined functional units with                     ability to handle branching, exceptions and global code motion,                 and a timing-resource model for the pipelined resources that will               facilitate retargetable code generation for the pipelined                       resources.                                                                                                                                                      The plan is to test the concepts using the research version of                  the retargetable microcode compiler developed in the Firmware                   Engineering Laboratory.  Since the control of most high                         performance computing engines is done at the firmware level, the                scheduling techniques are geared towards microcode                              implementations.  In order to accomplish the task of imbedding                  the pipeline schedules in the microcode one needs to develop a                  model for pipelined resources that facilitate the (retargetable)                microcode generation for the pipelined resources.                                                                                                               The significance of the proposed research lies in the pursuit of                the quality  (micro)coded control of the high performance,                      specialized computing engines.  Major application areas are:                    realtime digital signal processing, computer vision and graphics,               and related to these areas, specialized scientific computation.
{'FirstName': 'Jack', 'LastName': 'Walicki', 'EmailAddress': None, 'StartDate': '08/15/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Colorado State University', 'CityName': 'Fort Collins', 'ZipCode': '805232002', 'PhoneNumber': '9704916355', 'StreetAddress': '601 S Howes St', 'CountryName': 'United States', 'StateName': 'Colorado', 'StateCode': 'CO'}
{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8801889.xml'}