Presidential Young Investigator Award:  Automatic           Verification of Finite State Concurrent Systems
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{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
Dill         Research is on the verification of finite-state concurrent  systems, both abstract systems and their implementations in  hardware.  The approach is to represent the set of states as a  boolean function in the form of a binary decision diagram, then  find and inspect the set of states reachable from a set of  initial states.  A protocol description language and a  verification system are being developed and tested on real-world  designs.  Additionally, effort is being made to characterize  conditions under which verification is particularly attractive,  for example using it in the initial design phase when the system  is abstract.  Several benchmark examples for other users are  being developed.
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{'Name': 'Stanford University', 'CityName': 'STANFORD', 'ZipCode': '943052004', 'PhoneNumber': '6507232300', 'StreetAddress': '450 JANE STANFORD WAY', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '16', 'CONGRESS_DISTRICT_ORG': 'CA16', 'ORG_UEI_NUM': 'HJD6G4D6TJY5', 'ORG_LGL_BUS_NAME': 'THE LELAND STANFORD JUNIOR UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
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