Research Initiation:  Study of a New Built-in Self-Test     Architecture
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Gerald Maguire', 'PO_EMAI': None, 'PO_PHON': None}
A new built-in self-test architecture that can better exploit parallel          processing is being studied.  In conventional built-in self-test                algorithms, the pseudorandom pattern generators and signature registers         do not operate in parallel.  The goal of this research is to study a            new built-in self-test architecture that generates the test pattern for         one module while collecting responses of test patterns of other test            modules.  The resulting design will be area efficient, have parallel            testing, and have simple control circuity.                                                                                                                      With the rapid growth of VLSI technology and increased complexity of            VLSI circuits, conventional test methods in which the test patterns are         stored in test equipment and are applied to the external pins of the            chip may not be cost effective due to the poor accessibility to                 internal modes.  With a built-in self-test scheme, test patterns and            test response evaluators are placed in the same chip.  The research of          enhancing parallelism in built-in self-test is very important in                complex VLSI circuits.                                                          The principal investigator is a new Ph.D. who already has significant           progress in his research.  The research focuses on important and timely         topics.  Support is highly recommended.
{'FirstName': 'Dong', 'LastName': 'Ha', 'PI_MID_INIT': 'S', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Dong S Ha', 'EmailAddress': 'ha@vt.edu', 'NSF_ID': '000390358', 'StartDate': '06/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Virginia Polytechnic Institute and State University', 'CityName': 'BLACKSBURG', 'ZipCode': '240603359', 'PhoneNumber': '5402315281', 'StreetAddress': '300 TURNER ST NW', 'StreetAddress2': 'STE 4200', 'CountryName': 'United States', 'StateName': 'Virginia', 'StateCode': 'VA', 'CONGRESSDISTRICT': '09', 'CONGRESS_DISTRICT_ORG': 'VA09', 'ORG_UEI_NUM': 'QDE5UHE5XD16', 'ORG_LGL_BUS_NAME': 'VIRGINIA POLYTECHNIC INSTITUTE & STATE UNIVERSITY', 'ORG_PRNT_UEI_NUM': 'M515A1DKXAN8'}
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[{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}, {'Code': '4725', 'Text': 'EXPERIMENTAL SYSTEMS/CADRE'}, {'Code': '9120', 'Text': 'CROSS-DIRECTORATE PROGRAMS'}]
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