Research on Cache Memories
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Gerald Maguire', 'PO_EMAI': None, 'PO_PHON': None}
Memory hierarchy performance, and cache memory performance in                   particular, is the limiting factor in most or all modern computers.             The machine cycle time is usually limited by the cache access time.             Cache misses and slow main-memory access times significantly increase           mean instruction execution time.  Shared bus multiprocessor designs are         limited in overall performance by bus bandwidth, and bus traffic                declines with cache effectiveness.  Finally, multiprocessing in an              environment with caches requires a mechanism to maintain memory                 consistency.                                                                                                                                                    This research is focusing on a number of the following topics:  (1)             develop and evaluate hardware-based cache consistency algorithms, and           extend their utility beyond common bus design; (2) develop and evaluate         efficient algorithms for trace-driven simulation ıbeyond those already          known!; (3) quantify the effect of cache parameter selection; (4)               investigate the design and use of caches in a vector processor; (5)             study the effect of bus design ıin particular, the IEEE Futurebus               design! and its proper use to maximize performance; (6) further develop         and evaluate software-based cache consistency algorithms; (7)                   investigate the feasibility of virtually addressed cache designs in             realistic systems; (8) evaluate cache performance via hardware                  measurement; (9) further characterize program behavior and cache                workloads; (10) develop and evaluate better cache prefetch algorithms;          (11) examine possible optimizations for caches or ROMs with unchanging          code ıe.g. microcode caches!; (12) evaluate the utility and design of           instruction buffers in systems which may also have instruction caches;          (13) evaluate the utility of multilevel caches as a function of                 technology; (14) look at the most appropriate designs for cache                 controller chips; and (15) study TLB design.                                    This project focuses on a number of problems contributing to the                limitation of the performance of high-speed computers.  Results will            contribute to the alleviation of some of the bottlenecks.
{'FirstName': 'Alan', 'LastName': 'Smith', 'PI_MID_INIT': 'J', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Alan J Smith', 'EmailAddress': None, 'NSF_ID': '000149704', 'StartDate': '07/15/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of California-Berkeley', 'CityName': 'BERKELEY', 'ZipCode': '947101749', 'PhoneNumber': '5106433891', 'StreetAddress': '1608 4TH ST STE 201', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '12', 'CONGRESS_DISTRICT_ORG': 'CA12', 'ORG_UEI_NUM': 'GS3YEVSS12N6', 'ORG_LGL_BUS_NAME': 'REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8713274.xml'}