Research Initiation: Graph Abstractions for Concurrent      Processing
{'Code': '05010400', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Forbes D. Lewis', 'PO_EMAI': None, 'PO_PHON': None}
Concurrent systems with dynamic interprocess topology present a new             control problem in computer programming.  Currently programmers are             forced to describe topologies at a level analogous to that of the               pointer or the goto statement.  The investigator proposes the use of a          technology based on graph grammars to control interconnections in a             high-level, abstract manner.                                                                                                                                    The computational agents in our system communicate through sets of              ports.  Each port is connected to a set of other agents.  A graph               grammar is used to specify the class of legal topologies, which may be          altered by rewriting using a production in the grammar.  This may               change the connectivity of agents.  A high-level selection mechanism is         employed to enable an agent to select subsets of agents connected to            particular ports for communication.  Agents consist of a set of                 methods; when a message is received the appropriate method for                  processing that message is invoked.                                                                                                                             The research under this grant involves the investigation of language            features and programming environment support necessary for a graph-             grammar based approach to concurrent programming, the implementation of         the system both on shared-memory and message-passing architectures, and         the investigation of algorithms for the mapping of logical graph                topologies onto physical processor topologies.
{'FirstName': 'Simon', 'LastName': 'Kaplan', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Simon Kaplan', 'EmailAddress': None, 'PI_PHON': None, 'NSF_ID': '000295875', 'StartDate': '06/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Illinois at Urbana-Champaign', 'CityName': 'URBANA', 'ZipCode': '618013620', 'PhoneNumber': '2173332187', 'StreetAddress': '506 S WRIGHT ST', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Illinois', 'StateCode': 'IL', 'CONGRESSDISTRICT': '13', 'CONGRESS_DISTRICT_ORG': 'IL13', 'ORG_UEI_NUM': 'Y8CWNJRCNN91', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF ILLINOIS', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '2875', 'Text': 'SYSTEM SOFTWARE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8809479.xml'}