Research on Topological Design Tools for Structured Logic   Arrays
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Research continues on highly automated software tools which produce             VLSI-structured logic designs which are correct by construction.                Emphasis in the research is on synthesis of multilevel Boolean Networks         with the following specific research objectives:  satisfy all ;ita              priori;ro design rules, specifications, and constraints whenever                possible; and provide a unified theory of disparate logic synthesis             techniques, including 2-level logic minimization methods, local                 transformation, don't-care techniques, and others.  A longer-range              objective is an investigation of possible applications of these                 synthesis techniques at the functional level.  The final goal is                "silicon compilation," i.e., automated synthesis of a given behavioral          specification (e.g., system architecture and instruction set) into              specified target layout technologies.  Test cases of complete                   microprocessor synthesis are studied.
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{'Code': '9115', 'Text': 'AUTOMATION'}
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