Research Initiation:  Fault Tolerance Schemes for High      Performance WSI Processor Arrays
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
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The development of area efficient fault-tolerant wafer-scale                    integration architectures for very high performance processor                   arrays that specifically ensure short and bounded interconnection               lengths following restructuring is being carried out.  New yield                and performance models to realistically evaluate the designs are                being developed.  Semiconductor chips for matrix multiplication                 are being implemented through the MOSIS (Metal Oxide                            Semiconductor Implementation System) facility.  Performance                     approaching one billion floating point operations is expected.                                                                                                  Wafer-scale integration allows processors of high performance to                be developed. In such designs, interprocessor signals are not                   subject to off-chip propagation delays.  Issues on fault                        tolerance are especially important in such designs in order to                  overcome long delays caused by reconfiguration due to fabrication               defects.
{'FirstName': 'Adit', 'LastName': 'Singh', 'PI_MID_INIT': 'D', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Adit D Singh', 'EmailAddress': 'adsingh@eng.auburn.edu', 'NSF_ID': '000239664', 'StartDate': '06/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Massachusetts Amherst', 'CityName': 'AMHERST', 'ZipCode': '010039252', 'PhoneNumber': '4135450698', 'StreetAddress': '101 COMMONWEALTH AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Massachusetts', 'StateCode': 'MA', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'MA02', 'ORG_UEI_NUM': 'VGJHK59NMPK9', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF MASSACHUSETTS', 'ORG_PRNT_UEI_NUM': 'VGJHK59NMPK9'}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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