Research in Circuit Layout
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
As the density of components on a VLSI chip continues to grow, the need         to develop computer-aided tools for custom chips is crucial for the             continued advance of VLSI technology.  This research concentrates on            custom chip layout, an area in which major breakthrough is expected in          the next decade.  The aim here is to develop theoretical knowledge,             efficient algorithms, and experimental layout systems.  The long-term           plan is to develop a goal-oriented, hierarchical, building block system         (an automatic custom layout system for placement and routing in VLSI            design) for custom VLSI chips.  Logical design, simulation, and                 physical layout are run in parallel to reduce design time and produce           error-free layout.  Hierarchical simulators are to be integrated with a         hierarchical building block layout system.  System flexibility will             allow designer's intervention.
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[{'Code': '1453', 'Text': 'COMMU SYSTEMS & SIGNAL PROCESS'}, {'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}]
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