Very Large Scale Integration (VLSI) for Digital Signal      Processing
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{'SignBlockName': 'Helen A. Walston', 'PO_EMAI': None, 'PO_PHON': None}
Research is conducted on these aspects of very large scale integrated           (VLSI) design that are especially relevant to digital signal                    processing.  This research deals with the implementation of important           digital signal processing algorithms, such as linear filtering and              Fourier transformation, in custom VLSI circuit technology.  These               algorithms have a great deal of inherent structural regularity and it           is the objective of this work to exploit this regularity to increase            throughput and to make design and testing of signal processing chips            straightforward and easier.  In this investigation, automatic leaf-cell         (use of same cell in many instances) optimization, global performance           of regular structures, and testing of regular structures are being              pursued.  The long-range goal of this effort is to reduce the                   algorithmic structure to implementation on a chip in the most                   expeditious and efficient manner.
{'FirstName': 'Kenneth', 'LastName': 'Steiglitz', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Kenneth Steiglitz', 'EmailAddress': 'ken@princeton.edu', 'NSF_ID': '000192098', 'StartDate': '05/01/1985', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Princeton University', 'CityName': 'PRINCETON', 'ZipCode': '085442001', 'PhoneNumber': '6092583090', 'StreetAddress': '1 NASSAU HALL', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'New Jersey', 'StateCode': 'NJ', 'CONGRESSDISTRICT': '12', 'CONGRESS_DISTRICT_ORG': 'NJ12', 'ORG_UEI_NUM': 'NJ1YPQXQG7U5', 'ORG_LGL_BUS_NAME': 'THE TRUSTEES OF PRINCETON UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '1453', 'Text': 'COMMU SYSTEMS & SIGNAL PROCESS'}
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