Research Initiation:  Interconnect Delay and Clock Skew     Optimization in VLSI Circuits
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
Dr. Ciesielski is investigating methods for optimizing signal                   path delays and clock skew in VLSI circuits, with the aim of                    improving VLSI chip performance.  Specifically, the goal of this                research is to find efficient techniques for adjusting, or fine                 tuning, wiring delays in VLSI chips at the lowest level of                      physical design.  This will be accomplished by assigning                        conducting layers to interconnect wires and placing contacts                    (vias) at layer changes.  A model for the minimization of                       critical path delays is proposed, in which precise RC                           characteristics of interconnect wires and vias are taken into                   account.  This model will be extended to incorporate other                      objectives in the optimization of interconnect delay, such as the               minimization of clock skew, equalization of data path delays and                introduction of precisely controlled wire delays in data paths.
{'FirstName': 'Maciej', 'LastName': 'Ciesielski', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Maciej Ciesielski', 'EmailAddress': 'ciesiel@ecs.umass.edu', 'NSF_ID': '000209810', 'StartDate': '09/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Massachusetts Amherst', 'CityName': 'AMHERST', 'ZipCode': '010039252', 'PhoneNumber': '4135450698', 'StreetAddress': '101 COMMONWEALTH AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Massachusetts', 'StateCode': 'MA', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'MA02', 'ORG_UEI_NUM': 'VGJHK59NMPK9', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF MASSACHUSETTS', 'ORG_PRNT_UEI_NUM': 'VGJHK59NMPK9'}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8809838.xml'}