CAD (Computer-Aided Design) Tools for Designing Signal      Processors
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
The proposed research is directed toward development of an efficient            system of CAD tools which allow rapid and efficient implementation of a         class of VLSI architectures.  The proposers will limit the system to a          class of target architectures that is restricted, but still robust              enough to be of interest.  The target architectures are hierarchial             meshes, an extension of the systolic array class.  Their system will            also have signal processing as the target application area, since the           majority of CAD effort in the country is on VLSI circuits for signal            processing.  The proposed tools to support the design of target                 architectures do the functions:  module generation and multilevel logic         reduction; gate placement within a component; component placement               within the hierarchial mesh architecture, and tools to help with                circuit simulation, layout, verification, and test vector generation.           The tools will be designed so that they can be tuned to classes of              architectures other than hierarchial mesh.                                      VLSI (very large scale integration) is a recent field that explores how         to design highly complex integrated circuits and related electronic             systems.  Development of the field is important to the nation's                 competitive lead in electronics.  Research on tools, tool systems and           computer-aided design (CAD) methodologies is needed because existing            tools and design systems do not scale up to meet the possibilities of           today's VLSI technology.  Especially of interest is progress in                 automating the design process.  This proposal is aimed at the CAD               automation problem, and the results will advance our knowledge in this          field.  This research is aimed at transfer of the technology, since the         tools will be designed to integrate with standard, widely used software         such as Unix, VALID Logic workstations, the widely-used MAGIC tools             from Berkeley and MOSSIM from Xidex.  The co-principal investigators            have made important contributions to the CAD tools area.  They bring to         bear a useful blend of theoretical and practical talents.
[{'FirstName': 'Robert', 'LastName': 'Owens', 'PI_MID_INIT': 'M', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Robert M Owens', 'EmailAddress': None, 'NSF_ID': '000219946', 'StartDate': '09/01/1987', 'EndDate': None, 'RoleCode': 'Co-Principal Investigator'}, {'FirstName': 'Mary', 'LastName': 'Irwin', 'PI_MID_INIT': 'J', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Mary J Irwin', 'EmailAddress': 'mji@cse.psu.edu', 'NSF_ID': '000348527', 'StartDate': '09/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}]
{'Name': 'Pennsylvania State Univ University Park', 'CityName': 'UNIVERSITY PARK', 'ZipCode': '168021503', 'PhoneNumber': '8148651372', 'StreetAddress': '201 OLD MAIN', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Pennsylvania', 'StateCode': 'PA', 'CONGRESSDISTRICT': '15', 'CONGRESS_DISTRICT_ORG': 'PA15', 'ORG_UEI_NUM': 'NPM2J7MSCF61', 'ORG_LGL_BUS_NAME': 'THE PENNSYLVANIA STATE UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8701367.xml'}