Microelectronic Information Processing Systems
{'Code': '15030000', 'Directorate': {'Abbreviation': 'TIP', 'LongName': 'Dir for Tech, Innovation, & Partnerships'}, 'Division': {'Abbreviation': 'TI', 'LongName': 'Translational Impacts'}}
{'SignBlockName': 'Ritchie B. Coryell', 'PO_EMAI': None, 'PO_PHON': None}
This project is for exploratory research to determine the                       implementation  factors and parameters for a new VLSI cell invoking             redundant number arithmetic instead of 1's/2's complement.  A narrow            application towards signal processing (multiply/accumulate intensive)           shall drive minimal area and speed designs.  Carry/borrow free designs          may greatly enhance modular fault-tolerant implementations.  For                further focus, the efficient Signed Binary Number Representation (SBNR)         as a tri-valued subset of general redundant number representations              affords more improved area/speed FOM's, thus making such cells highly           VLSI-regular.  This application specific study shall identify critical          design parameters (minimal line widths, functional partitioning, VIA's          , number of gates, inter/intracell connections) to aid the design               engineer.  Focus is on lower levels of computer architecture coupled to         technology/implementation issues where significant discoveries may be           leveraged into practical systolic arrays exceeding the design                   performance of GAPP and DAP devices while achieving breakthroughs in            minimal cell layouts.                                                           There is potential for an order of magnitude speedup of signal                  processing circuits through the use of non-conventional number system           implementations.  This project will focus on VLSI enhancements of               redundant number systems.  The latter have been studied extensively and         the time is ripe to assess their merit in circuit design.  This                 research topic is an excellent one for a small business to pursue               because of the potential for making a meaningful advance in the theory          and practice of signal processing circuit design.
{'FirstName': 'Michael', 'LastName': 'Andrews', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Michael Andrews', 'EmailAddress': None, 'PI_PHON': '3032211122', 'NSF_ID': '000190867', 'StartDate': '02/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Space Tech Corporation', 'CityName': 'Fort Collins', 'ZipCode': '805253934', 'PhoneNumber': None, 'StreetAddress': '125 Crestridge Drive', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Colorado', 'StateCode': 'CO', 'CONGRESSDISTRICT': '02', 'CONGRESS_DISTRICT_ORG': 'CO02', 'ORG_UEI_NUM': None, 'ORG_LGL_BUS_NAME': None, 'ORG_PRNT_UEI_NUM': None}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '5371', 'Text': 'SBIR Phase I'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8760094.xml'}