Avalanche Complementary Metal Oxide Semiconductor Logic:  A High Speed Differential Circuit
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{'SignBlockName': 'Ritchie B. Coryell', 'PO_EMAI': None, 'PO_PHON': None}
CMOS (Complementary Metal Oxide Semiconductor) technology is in                 widespread use.  However, a problem with CMOS logic circuits is low             speed of operation, especially compared to competing (but less                  technically desirable) technologies such as Emitter Coupled Logic.              Speed of operation can be increased if the effect of capacitances is            minimized.  In Phase I the principal investigator investigated                  capacitance minimization by operating CMOS logic circuits with voltage          swings as small as reliability considerations (noise) will permit.  He          found a design technique which limits noise generated by the logic              circuit itself.  The objective of Phase II is to validate                       experimentally an innovative logic circuit capable of operating several         fold faster than conventional circuits.  He will layout, simulate,              fabricate prototype chips, and measure the performance of a                     conventional (Manchester) 16-bit adder and a novel CMOS Avalanche CMOS          16-bit adder.  Worst case propagation delay, cycle time and power               dissipation will be measured.  It is anticipated that the Avalanche             adder will be four times faster than the conventional one.                      This proposal received high ratings on all SBIR Phase II evaluation             points, which are as follows.                                                                                                                                   1.   Phase I objectives were met completely with excellent                           results.                                                                   2.   This design technique has technical importance and is likely                    to be applicable to a variety of CMOS circuit designs.                     3.   Phase II objectives are appropriate and attainable.                        4.   Scientific and engineering quality is high.                                5.   The principal investigator is highly qualified to do the                        work, and he has made important contributions in the past.                 6.   The budget is commensurate with thorough Phase II                               investigation.                                                                                                                                                                                                                             Successful research by the principal investigator will result in high           likelihood of a desirable product, a significantly faster CMOS adder,           as well as a practical design technique for CMOS circuits.
{'FirstName': 'Constantin', 'LastName': 'Timoc', 'PI_MID_INIT': 'C', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Constantin C Timoc', 'EmailAddress': 'ctimoc@aol.com', 'PI_PHON': '8189520126', 'NSF_ID': '000127489', 'StartDate': '06/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Spaceborne Inc', 'CityName': 'La Canada', 'ZipCode': '910113406', 'PhoneNumber': '8189520126', 'StreetAddress': '742 Foothill Blvd. Suite 2B', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '28', 'CONGRESS_DISTRICT_ORG': 'CA28', 'ORG_UEI_NUM': None, 'ORG_LGL_BUS_NAME': None, 'ORG_PRNT_UEI_NUM': None}
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{'Code': '5373', 'Text': 'SBIR Phase II'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8721764.xml'}