Research Initiation:  Development of Testing and Simulation Methodologies  for Infant Failure and Field-Yield Estimationfor MOS VLSI/ULSI Circuits
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Gerald Maguire', 'PO_EMAI': None, 'PO_PHON': None}
New switch-level approaches for fast and efficient simulation of                MOS IC's are to be formulated in order to estimate "infant"                     (i.e., early) failures and to estimate field yield in large                     chips.  The simulation scheme is also expected to identify the                  critical sub-section of circuits that cause early failures and                  should help in redesigning for greater robustness.
{'FirstName': 'Bharat', 'LastName': 'Bhuva', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Bharat Bhuva', 'EmailAddress': 'bharat.bhuva@vanderbilt.edu', 'NSF_ID': '000251700', 'StartDate': '08/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Vanderbilt University', 'CityName': 'NASHVILLE', 'ZipCode': '372032416', 'PhoneNumber': '6153222631', 'StreetAddress': '110 21ST AVE S', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Tennessee', 'StateCode': 'TN', 'CONGRESSDISTRICT': '05', 'CONGRESS_DISTRICT_ORG': 'TN05', 'ORG_UEI_NUM': 'GTNBNWXJ12D5', 'ORG_LGL_BUS_NAME': 'VANDERBILT UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
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