Architectures for Error Control in VLSI Random Access MemorySystems
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The aim of this research is to investigate the role and form that error         control should take in the design of future random access memory (RAM)          systems. A system-wide hierarchic approach to the problem is being              pursued.  Both on-chip and board-level error control are being explored         with a focus on assessing the effectiveness of each in controlling              various error sources and the impact each layer has on the other.  The          research includes (1) Coding Techniques:  construction of error-control         codes with qualities suited for RAM protection; (2) VLSI Architectures:         the design and fabrication of VLSI circuits that implement these codes;         and (3) Performance Analysis:  mathematical analysis of the                     effectiveness of these codes and the complexity of their                        implementation.                                                                 The end result of the research will be a better understanding of how to         construct computer memories that are larger, faster and more reliable           than those being designed today.  It will demonstrate how error control         can be used to keep the reliability of RAM systems high even as chip            feature sizes shrink and multi-megabit chips become common.  This               research is a collaborative effort with Dr. Chris Heegard of Cornell            University
{'FirstName': 'Rodney', 'LastName': 'Goodman', 'PI_MID_INIT': 'M', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Rodney M Goodman', 'EmailAddress': 'rogo@caltech.edu', 'NSF_ID': '000463891', 'StartDate': '02/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'California Institute of Technology', 'CityName': 'PASADENA', 'ZipCode': '911250001', 'PhoneNumber': '6263956219', 'StreetAddress': '1200 E CALIFORNIA BLVD', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '28', 'CONGRESS_DISTRICT_ORG': 'CA28', 'ORG_UEI_NUM': 'U2JMKHNS5TG4', 'ORG_LGL_BUS_NAME': 'CALIFORNIA INSTITUTE OF TECHNOLOGY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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