Research on Layout, Interconnection, and Testing
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
This research covers VLSI physical design problems:  macrocell-                 based custom chip layout, interconnection within and between VLSI               chips, and design for testability.  Layout problems are                         considered within a hierarchical automatic building-block layout                system.  The problems are on timing-driven layout and optimum                   layout of power and ground nets.  The later problem is considered               for the case of three metal layers.  Theory and algorithms for                  interconnection problems are being pursued; and two specific                    problems are being solved.  These are:  three-dimensional module                interconnect including estimates of length and space, and global                and detailed routing.  Also being considered are problems in                    routing methodology for long-wire dominated custom chips and                    routing for wafer-scale integration.  Research at the interface                 between layout and testing is being addressed.  In particular,                  validation of assumptions made for design for testability and                   reduction of hard-to-detect faults through layout are being                     investigated.  Computational geometry is being used to understand               the problem of designing repairable arrays.
{'FirstName': 'Ernest', 'LastName': 'Kuh', 'PI_MID_INIT': 'S', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Ernest S Kuh', 'EmailAddress': None, 'NSF_ID': '000202616', 'StartDate': '12/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of California-Berkeley', 'CityName': 'BERKELEY', 'ZipCode': '947101749', 'PhoneNumber': '5106433891', 'StreetAddress': '1608 4TH ST STE 201', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '12', 'CONGRESS_DISTRICT_ORG': 'CA12', 'ORG_UEI_NUM': 'GS3YEVSS12N6', 'ORG_LGL_BUS_NAME': 'REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE', 'ORG_PRNT_UEI_NUM': None}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
[{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}, {'Code': '9120', 'Text': 'CROSS-DIRECTORATE PROGRAMS'}, {'Code': '9145', 'Text': 'SPECIAL PROGRAMS-RESERVE'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1988&All=true', 'xml': '8803711.xml'}