Efficient Execution of Dataflow Programs
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Yechezkel Zalcstein', 'PO_EMAI': 'zzalcste@nsf.gov', 'PO_PHON': '7032920000'}
A number of architectures have been proposed to implement the basic             principles of dataflow computation.  The main problem common to all             these architectures is a large overhead associated with the execution           of each individual instruction.  In particular, each operand that               passes from one instruction to another may have to travel considerable          distances through a communication network and various hardware                  components (special memories and queues) before it reaches its                  destination.  Furthermore, operands destined for the same instruction           must be recognized and segregated in a special token matching store.            Only when all operands have arrived for an instruction, can it be               scheduled for execution on a processor.  In comparison, passing an              operand from one instruction to another in a von Neumann computer               requires only a simple memory store operation.                                                                                                                  In this research, a different approach is used to executing dataflow            program, which significantly reduces the overhead of operand routing            and matching.  The approach is based on the idea of breaking a given            dataflow program into segments of code which, due to their operand              dependencies, must be executed sequentially.  Each such sequence may be         loaded into memory for execution whenever its first instruction is              enabled.  Once loaded,it can be viewed as a very simple sequential              process, which is ready when its current instruction is enabled,                running when there is a free processor, and blocked when its current            instruction is waiting for operands to arrive.  Hence, the dataflow             program may be viewed as a collection of very simple communicating              processes.                                                                                                                                                      In this research, they will investigate the process-oriented approach           by formulating the model and the architecture in more detail and by             performing extensive simulation experiments to compare its performance          to von Neumann computers and to other dataflow systems.
{'FirstName': 'Lubomir', 'LastName': 'Bic', 'PI_MID_INIT': 'F', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Lubomir F Bic', 'EmailAddress': 'bic@ics.uci.edu', 'NSF_ID': '000453349', 'StartDate': '08/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of California-Irvine', 'CityName': 'IRVINE', 'ZipCode': '926970001', 'PhoneNumber': '9498247295', 'StreetAddress': '160 ALDRICH HALL', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '47', 'CONGRESS_DISTRICT_ORG': 'CA47', 'ORG_UEI_NUM': 'MJC5FCYQTPE6', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF CALIFORNIA IRVINE', 'ORG_PRNT_UEI_NUM': 'MJC5FCYQTPE6'}
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{'Code': '471500', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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