Multiprocessor-Based VLSI (Very Large Scale Integrated)     Layout Algorithms
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
Dr. Rutenbar will investigate VLSI design layout tasks that can be              structured as combinatorial optimization problems and solved with               parallel simulated annealing algorithms.  Two sorts of multi-processors         are becoming available:  shared memory and distributed memory machines.         The research will consider running parallel algorithms on distributed           memory machines.  This is because parallel simulated annealing in shared        memory machines tends to be conceptually easier and has received more           attention than in distributed memory machines.  The research will build         on an operational floor-planner, which the principal investigator has           recently built. It will be the vehicle for testing new ideas for                algorithm decompositions and different styles of parallel simulated             annealing.  This work will be carefully instrumented and measured to            identify and quantify important effects on speedup and solution quality.        After the experimentation and measurement phase, the principal                  investigator will develop models of how speedup and solution quality are        effected by different styles of parallelism.  The goal is to gain               sufficient knowledge of parallel simulated annealing in general to              permit reasonable control of the process applied to a range of VLSI             design problems.                                                                Very and ultra large scale integrated (VLSI/ULSI) circuit design has            become a topic of intense interest in the research community and                practical interest to engineers and scientists.  This research addresses        the need to run sophisticated design algorithms for ULSI circuit design.        It is a need that has become of paramount importance as such devices            become increasingly complex and the industry more competitive.  To do           this in a reasonable amount of time, it is necessary to consider the            speedup that running the design software on parallel computers.  This           entails development of new algorithms which run efficiently on parallel         machines.  A general method for running algorithms on parallel machines         is called "simulated annealing".  This method, while conceptually               simple, does not have obvious implementations for VLSI/ULSI design              algorithms. The principal investigator has made important conceptual            advances in this area and will further develop them toward practice in          his research.
{'FirstName': 'Rob', 'LastName': 'Rutenbar', 'PI_MID_INIT': 'A', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Rob A Rutenbar', 'EmailAddress': 'rutenbar@ece.cmu.edu', 'NSF_ID': '000328485', 'StartDate': '07/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Carnegie-Mellon University', 'CityName': 'PITTSBURGH', 'ZipCode': '152133815', 'PhoneNumber': '4122688746', 'StreetAddress': '5000 FORBES AVE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Pennsylvania', 'StateCode': 'PA', 'CONGRESSDISTRICT': '18', 'CONGRESS_DISTRICT_ORG': 'PA18', 'ORG_UEI_NUM': 'U3NKNFLNQ613', 'ORG_LGL_BUS_NAME': 'CARNEGIE MELLON UNIVERSITY', 'ORG_PRNT_UEI_NUM': 'U3NKNFLNQ613'}
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{'Code': '4710', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
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