Performance-Oriented Logic Synthesis
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'John R. Lehmann', 'PO_EMAI': None, 'PO_PHON': None}
Automatic synthesis of digital circuits is pivotal for the design of            integrated circuits with fast turn-around time.  The quality of the             synthesized circuits is measured by some figures of merit, such as, for         example, silicon area, power consumption and switching-time performance.        This project addresses the trade-offs in area (power) minimality and            switching-time optimality.  In particular, the search for a set of              circuit transformations which can transform a circuit that is optimal in        terms of area into another that is optimal in terms of timing.  The             objectives of the research are:  (1) study a graph/algebraic model of           combinational logic circuits; (2) use the model to define circuit               transformations and determine their properties; (3) implement these             transformations as a CAD tool program which can be used interactively           (or not) in the search of good trade-off points between area (power) and        timing.                                                                                                                                                         The theoretical part of this research is centered on algorithms based on        graph theory and algebraic properties of Boolean functions.  The                experimental part addresses a computer implementation of the algorithms         and their test on real circuit design examples.                                 The impact of this research may be very profound on the CAD and designer        community.  Algorithms for synthesis and optimization of multiple-level         logic are in high demand.  The problem is well defined but not as well          understood.  Designers still rely on their ingenious expertise but              cannot be supported yet by a well-defined theory based on sound                 mathematical foundations.
{'FirstName': 'Giovanni', 'LastName': 'De Micheli', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Giovanni De Micheli', 'EmailAddress': 'nanni@stanford.edu', 'NSF_ID': '000462092', 'StartDate': '07/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Stanford University', 'CityName': 'STANFORD', 'ZipCode': '943052004', 'PhoneNumber': '6507232300', 'StreetAddress': '450 JANE STANFORD WAY', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'California', 'StateCode': 'CA', 'CONGRESSDISTRICT': '16', 'CONGRESS_DISTRICT_ORG': 'CA16', 'ORG_UEI_NUM': 'HJD6G4D6TJY5', 'ORG_LGL_BUS_NAME': 'THE LELAND STANFORD JUNIOR UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
{'Name': None, 'CityName': None, 'StateCode': None, 'ZipCode': None, 'StreetAddress': None, 'CountryCode': None, 'CountryName': None, 'StateName': None, 'CountryFlag': None, 'CONGRESSDISTRICT': None, 'CONGRESS_DISTRICT_PERF': '""'}
{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1987&All=true', 'xml': '8710748.xml'}