Fault Tolerant Highly Parallel Signal Processing            Architectures
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
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The availability of low-cost, high-density, high-speed processors               and memories in VLSI, together with the increasing demands for                  high-performance in signal processing, has resulted in numerous                 proposals for highly parallel signal processing architectures.                  Since reliability is a key requirement, this research addresses                 the issues involved in the design of fault tolerance features in                these parallel architectures. The specific, unique and promising                approach to fault tolerance in this project is the use of low-                  cost on-line system-level error detection and correction                        techniques, which are tailored to the signal processing                         algorithms being executed on these architectures.  Novel encoding               schemes for various classes of signal processing algorithms are                 being explored.  The effects of mapping large problems on limited               processor mesh-connected architectures are being investigated                   from the viewpoint of algorithm-based checking.  The effects of                 finite precision arithmetic on system level encodings are being                 studied.  The fault coverage and reliability improvements due to                algorithm-based checking schemes are being investigated using                   analytical techniques as well as functional simulations.                        Eventually, the research should result in the identification of                 some basic principles for the design of algorithm-based fault                   tolerance techniques.
{'FirstName': 'Prithviraj', 'LastName': 'Banerjee', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Prithviraj Banerjee', 'EmailAddress': 'prith@uic.edu', 'PI_PHON': '3129962400', 'NSF_ID': '000306284', 'StartDate': '01/01/1988', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Illinois at Urbana-Champaign', 'CityName': 'URBANA', 'ZipCode': '618013620', 'PhoneNumber': '2173332187', 'StreetAddress': '506 S WRIGHT ST', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Illinois', 'StateCode': 'IL', 'CONGRESSDISTRICT': '13', 'CONGRESS_DISTRICT_ORG': 'IL13', 'ORG_UEI_NUM': 'Y8CWNJRCNN91', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF ILLINOIS', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1986&All=true', 'xml': '8619121.xml'}