Presidential Young Investigator Award:High Performance      Parallel Processing Systems
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Yechezkel Zalcstein', 'PO_EMAI': 'zzalcste@nsf.gov', 'PO_PHON': '7032920000'}
The underlying theme of current research is development of a high-              performance parallel processing system based on large numbers (hundreds         or thousands) of microcomputers.  Such a parallel system would consist          of interconnected computing nodes that asynchronously cooperate via             message passing to execute the tasks of parallel programs.  Each                network node, fabricated as a small number of VLSI chips, would in turn         contain a processor, a local memory, and a communication controller             capable of routing messages without delaying the computation processor.         This approach to parallel computation, like all others, poses many              vexing problems, including hardware design, operating system and                programming support software, and algorithm design.  Although there are         interests in all areas of message-based parallel computation, their             primary research areas are operating system design and performance              directed algorithm design.                                                                                                                                      In collaboration with the concurrent computation project at the Jet             Propulsion Laboratory, they are currently developing several classes of         dynamic scheduling algorithms.  Among these is one group based on               experience with adaptive packet routing algorithms.                                                                                                             In addition to their work in dynamic task scheduling, the research team         is developing a set of performance models for message passing machines          analogous to those used with vector processors.  These models have been         used to predict the performance of problem partitioning strategies for          solution of partial differential equations; independent implementation          of the partitioning strategies has confirmed the accuracy of their              technique.
{'FirstName': 'Daniel', 'LastName': 'Reed', 'PI_MID_INIT': 'A', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Daniel A Reed', 'EmailAddress': 'dan.reed@utah.edu', 'NSF_ID': '000356566', 'StartDate': '07/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Illinois at Urbana-Champaign', 'CityName': 'URBANA', 'ZipCode': '618013620', 'PhoneNumber': '2173332187', 'StreetAddress': '506 S WRIGHT ST', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Illinois', 'StateCode': 'IL', 'CONGRESSDISTRICT': '13', 'CONGRESS_DISTRICT_ORG': 'IL13', 'ORG_UEI_NUM': 'Y8CWNJRCNN91', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF ILLINOIS', 'ORG_PRNT_UEI_NUM': None}
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[{'Code': '257000', 'Text': None}, {'Code': '471500', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}]
{'url': 'https://www.nsf.gov/awardsearch/download?DownloadFileName=1986&All=true', 'xml': '8657696.xml'}