Memory Hierarchy in MIMD Multiprocessors
{'Code': '05010300', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Yechezkel Zalcstein', 'PO_EMAI': 'zzalcste@nsf.gov', 'PO_PHON': '7032920000'}
The research team intends to study the management of the memory                 hierarchy in MIMD multiprocessors.  The recent technological explosion          has allowed the inclusion of large and fast memories in many levels of          the memory hierarchy.  The management of this hierarchy is quite well           understood in a uniprocessor environment but newer challenges present           themselves in a multiprocessor system.                                                                                                                          One of these challenges is the cache coherence problem.  They will              continue previous studies on cache coherence in shared-bus systems              (enhancement of existing solutions with software hints, evaluation on           specific applications)  and in interconnected systems (they will model          a wide spectrum of solutions).                                                                                                                                  They will extend these studies with those pertaining to the design and          management of the memory hierarchy in high-performance systems.  This           will include multilevel caches (architectural choices, design and               evaluation of protocols) and systems where not all levels are managed           under the virtual memory concept (use of planned transfers of data              between memory levels with compiler and programmer assists).                                                                                                    Finally, they will try to evaluate qualitatively and quantitatively the         numerous possibilities for the location of the translation buffer from          the conventional real caches to those architectures using virtual               address caches.
{'FirstName': 'Jean-Loup', 'LastName': 'Baer', 'PI_MID_INIT': None, 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Jean-Loup Baer', 'EmailAddress': 'baer@cs.washington.edu', 'NSF_ID': '000469844', 'StartDate': '08/01/1987', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'University of Washington', 'CityName': 'SEATTLE', 'ZipCode': '981951016', 'PhoneNumber': '2065434043', 'StreetAddress': '4333 BROOKLYN AVE NE', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'Washington', 'StateCode': 'WA', 'CONGRESSDISTRICT': '07', 'CONGRESS_DISTRICT_ORG': 'WA07', 'ORG_UEI_NUM': 'HD1WMN6945W6', 'ORG_LGL_BUS_NAME': 'UNIVERSITY OF WASHINGTON', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '4715', 'Text': 'COMPUTER SYSTEMS ARCHITECTURE'}
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