Design for Robust Testability of CMOS VLSI Circuits
{'Code': '05010600', 'Directorate': {'Abbreviation': 'CSE', 'LongName': 'Direct For Computer & Info Scie & Enginr'}, 'Division': {'Abbreviation': 'CCF', 'LongName': 'Division of Computing and Communication Foundations'}}
{'SignBlockName': 'Robert B Grafton', 'PO_EMAI': None, 'PO_PHON': None}
This research is to develop test procedures for robust testing and              design for testability (DFT) of CMOS circuits.  The most likely faults          in CMOS circuits are stuck-open, stuck-at and bridging faults.  Thus            the traditional stuck-at fault model is inadequate for MOS                      Technologies.  Furthermore, a test set for a CMOS circuit may be                invalidated by arbitrary delay signals and charge distribution among            the internal nodes of the CMOS gates in the circuit.  Professor Jha is          developing methods to generate test sets to robustly test for faults in         spite of delays and charge distribution.  His approach is based on two-         pattern tests to detect faults from a comprehensive fault model via             logic and current monitoring.  This avoids an increase in test                  generation time in order to gain comprehensive fault coverage.  The DFT         research is based on a theoretical result of Professor Jha that a               universal test set can be found which is valid for all implementations          from a class of CMOS circuits.  Finally, testing issues related to              dynamic CMOS circuits are being investigated because they enjoy the             advantage of greater testability over fully complementary CMOS                  circuits.
{'FirstName': 'Niraj', 'LastName': 'Jha', 'PI_MID_INIT': 'K', 'PI_SUFX_NAME': None, 'PI_FULL_NAME': 'Niraj K Jha', 'EmailAddress': 'jha@princeton.edu', 'NSF_ID': '000123477', 'StartDate': '03/01/1989', 'EndDate': None, 'RoleCode': 'Principal Investigator'}
{'Name': 'Princeton University', 'CityName': 'PRINCETON', 'ZipCode': '085442001', 'PhoneNumber': '6092583090', 'StreetAddress': '1 NASSAU HALL', 'StreetAddress2': None, 'CountryName': 'United States', 'StateName': 'New Jersey', 'StateCode': 'NJ', 'CONGRESSDISTRICT': '12', 'CONGRESS_DISTRICT_ORG': 'NJ12', 'ORG_UEI_NUM': 'NJ1YPQXQG7U5', 'ORG_LGL_BUS_NAME': 'THE TRUSTEES OF PRINCETON UNIVERSITY', 'ORG_PRNT_UEI_NUM': None}
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{'Code': '471000', 'Text': 'DES AUTO FOR MICRO & NANO SYS'}
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