The context register made no distinction between user and supervisor states; interrupts and traps did not switch contexts which required that all valid interrupt vectors always be mapped in page 0 of context, as well as the valid Supervisor Stack.
The context register made no distinction between user and supervisor states. Interrupts and traps did not switch contexts, as well as the valid Supervisor Stack. All valid interrupt vectors always be mapped in page 0 of context. These contexts required this.