that the boasting happens or the Gallicness does not occur or both is not correct.
sent1: the branchiateness occurs. sent2: if the angriness does not occur then that both the amplitude and the antemortemness happens is not right. sent3: the branchiateness does not occur if that the premeditating happens and the dueness happens is true. sent4: if the adjustment does not occur and the branchiateness does not occur the premeditating does not occur. sent5: if the fact that either the boast occurs or the Gallicness happens or both is wrong the angriness occurs. sent6: either the anoxicness happens or the sediment does not occur or both. sent7: the chylificness does not occur. sent8: the angriness occurs if that either the boast happens or the Gallicness does not occur or both is wrong. sent9: the premeditating does not occur if that the antemortemness does not occur is true. sent10: if the half-light does not occur and the uploading mandarin occurs the generation does not occur. sent11: the boast and/or the Gallicness occurs. sent12: that the paradigmaticness happens is prevented by that not the regular but the irregularness occurs. sent13: that the premeditating does not occur but the dueness happens is caused by that the antemortemness does not occur. sent14: the Gallicness happens. sent15: the non-branchiateness is triggered by that not the premeditating but the due happens. sent16: if the angriness occurs the amplitude occurs. sent17: the antemortemness does not occur if the fact that the amplitude happens is not false. sent18: the fact that the premeditating does not occur is true.
void -> assump1: Let's assume that that the boast occurs or the Gallicness does not occur or both is not correct.; sent8 & assump1 -> int1: the angriness occurs.; int1 & sent16 -> int2: the fact that the amplitude occurs is not incorrect.; int2 & sent17 -> int3: the antemortemness does not occur.; int3 & sent13 -> int4: not the premeditating but the due happens.; int4 & sent15 -> int5: the branchiateness does not occur.; int5 & sent1 -> int6: this is contradiction.; [assump1] & int6 -> hypothesis;
that the boasting happens or the Gallicness does not occur or both is not correct.
$hypothesis$ = that the boasting happens or the Gallicness does not occur or both is not correct. ; $context$ = sent1: the branchiateness occurs. sent2: if the angriness does not occur then that both the amplitude and the antemortemness happens is not right. sent3: the branchiateness does not occur if that the premeditating happens and the dueness happens is true. sent4: if the adjustment does not occur and the branchiateness does not occur the premeditating does not occur. sent5: if the fact that either the boast occurs or the Gallicness happens or both is wrong the angriness occurs. sent6: either the anoxicness happens or the sediment does not occur or both. sent7: the chylificness does not occur. sent8: the angriness occurs if that either the boast happens or the Gallicness does not occur or both is wrong. sent9: the premeditating does not occur if that the antemortemness does not occur is true. sent10: if the half-light does not occur and the uploading mandarin occurs the generation does not occur. sent11: the boast and/or the Gallicness occurs. sent12: that the paradigmaticness happens is prevented by that not the regular but the irregularness occurs. sent13: that the premeditating does not occur but the dueness happens is caused by that the antemortemness does not occur. sent14: the Gallicness happens. sent15: the non-branchiateness is triggered by that not the premeditating but the due happens. sent16: if the angriness occurs the amplitude occurs. sent17: the antemortemness does not occur if the fact that the amplitude happens is not false. sent18: the fact that the premeditating does not occur is true. ; $proof$ = 
void -> assump1: Let's assume that that the boast occurs or the Gallicness does not occur or both is not correct.; sent8 & assump1 -> int1: the angriness occurs.; int1 & sent16 -> int2: the fact that the amplitude occurs is not incorrect.; int2 & sent17 -> int3: the antemortemness does not occur.; int3 & sent13 -> int4: not the premeditating but the due happens.; int4 & sent15 -> int5: the branchiateness does not occur.; int5 & sent1 -> int6: this is contradiction.; [assump1] & int6 -> hypothesis; __DISPROVED__