src/bins/decode.cc
void Decode::DecodeIzpY(CpuOperation op) {
  state_->AddCycle(MEM_READZP | MEM_OP1(REG_TMP1) | MEM_ADDR(REG_PCL) | PC_INC);
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRL) | MEM_ADDR(REG_TMP1));
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRH) | MEM_ADDR(REG_TMP1)
                                                 | MEM_OFST(1)
                 | DAT_ADD | DAT_DST(REG_ADDRL) | DAT_SRC(REG_Y));
  state_->AddCycle(MEM_READ | MEM_OP1(REG_TMP1) | MEM_ADDR(REG_ADDRL)
                 | DAT_VFIX | DAT_DST(REG_ADDRH) | DAT_SRC(REG_TMP2));
  state_->AddCycle(MEM_FETCH | op | PC_INC);
  return;
}
/*
 * Queues an indirect indexed zero page read instruction using the given micro
 * operation.
 */
Queues an indirect indexed zero page read instruction using the given micro
operation.
Queues an indirect indexed zero page read instruction using the given micro operation .
void Decode::DecodeIzpY(CpuOperation op) {
  state_->AddCycle(MEM_READZP | MEM_OP1(REG_TMP1) | MEM_ADDR(REG_PCL) | PC_INC);
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRL) | MEM_ADDR(REG_TMP1));
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRH) | MEM_ADDR(REG_TMP1)
                                                 | MEM_OFST(1)
                 | DAT_ADD | DAT_DST(REG_ADDRL) | DAT_SRC(REG_Y));
  state_->AddCycle(MEM_READ | MEM_OP1(REG_TMP1) | MEM_ADDR(REG_ADDRL)
                 | DAT_VFIX | DAT_DST(REG_ADDRH) | DAT_SRC(REG_TMP2));
  state_->AddCycle(MEM_FETCH | op | PC_INC);
  return;
}
void Decode :: DecodeIzpY ( CpuOperation op ) { state_ -> AddCycle ( MEM_READZP | MEM_OP1 ( REG_TMP1 ) | MEM_ADDR ( REG_PCL ) | PC_INC ) ; state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_ADDRL ) | MEM_ADDR ( REG_TMP1 ) ) ; state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_ADDRH ) | MEM_ADDR ( REG_TMP1 ) | MEM_OFST ( 1 ) | DAT_ADD | DAT_DST ( REG_ADDRL ) | DAT_SRC ( REG_Y ) ) ; state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_TMP1 ) | MEM_ADDR ( REG_ADDRL ) | DAT_VFIX | DAT_DST ( REG_ADDRH ) | DAT_SRC ( REG_TMP2 ) ) ; state_ -> AddCycle ( MEM_FETCH | op | PC_INC ) ; return ; }
Queues an indirect indexed zero page read instruction using the given micro
 operation.
Queues an indirect indexed zero page read instruction using the given micro operation .