The data address space consists of the register file, I/O registers, and SRAM. The tag specified one of three index registers. These are separate from the integer registers. It schedules access to the registers or memory that will get the results. Each of the MMn registers are 64-bit integers. The CPU has eight 32-bit general-purpose data registers (D0-D7), and eight address registers (A0-A7). The 1000 words of memory consisted of 100 channels of 10-word mercury delay line registers. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The segment selector must be located in one of the segment registers. It had only six registers plus condition indicators, and no stack. This disaster destroyed all the registers and records. The output, therefore, registers a high voltage. The ear transforms this movement into neural signals that the brain registers as sound. Designers also experimented with using large sets of internal registers. A few instructions operate on pairs of registers.