{"action":"closed","issue":{"url":"https://api.github.com/repos/mofosyne/arduino-gameboy-printer-emulator/issues/7","repository_url":"https://api.github.com/repos/mofosyne/arduino-gameboy-printer-emulator","labels_url":"https://api.github.com/repos/mofosyne/arduino-gameboy-printer-emulator/issues/7/labels{/name}","comments_url":"https://api.github.com/repos/mofosyne/arduino-gameboy-printer-emulator/issues/7/comments","events_url":"https://api.github.com/repos/mofosyne/arduino-gameboy-printer-emulator/issues/7/events","html_url":"https://github.com/mofosyne/arduino-gameboy-printer-emulator/issues/7","id":263857826,"number":7,"title":"Document `Everything You Always Wanted To Know About GAMEBOY` as it is missing in http://www.huderlem.com/demos/gameboy2bpp.html","user":{"login":"mofosyne","id":827793,"avatar_url":"https://avatars2.githubusercontent.com/u/827793?v=4","gravatar_id":"","url":"https://api.github.com/users/mofosyne","html_url":"https://github.com/mofosyne","followers_url":"https://api.github.com/users/mofosyne/followers","following_url":"https://api.github.com/users/mofosyne/following{/other_user}","gists_url":"https://api.github.com/users/mofosyne/gists{/gist_id}","starred_url":"https://api.github.com/users/mofosyne/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mofosyne/subscriptions","organizations_url":"https://api.github.com/users/mofosyne/orgs","repos_url":"https://api.github.com/users/mofosyne/repos","events_url":"https://api.github.com/users/mofosyne/events{/privacy}","received_events_url":"https://api.github.com/users/mofosyne/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2017-10-09T11:07:25Z","updated_at":"2017-12-03T02:13:35Z","closed_at":"2017-12-03T02:13:35Z","author_association":"OWNER","body":"\r\nhttp://www.huderlem.com/demos/gameboy2bpp.html\r\n\r\n```\r\n============================================================================\r\n            Everything You Always Wanted To Know About GAMEBOY *\r\n============================================================================\r\n\r\n                        * but were afraid to ask\r\n\r\n\r\n             Pan of -ATX- Document Updated by contributions from:\r\n          Marat Fayzullin, Pascal Felber, Paul Robson, Martin Korth\r\n\r\n                      Last update 12-Mar-98 by kOOPa\r\n\r\n Forward: The following was typed up for informational purposes regarding\r\n          the inner workings on the hand-held game machine known as\r\n          GameBoy, manufactured and designed by Nintendo Co., LTD.\r\n          This info is presented to inform a user on how their Game Boy\r\n          works and what makes it \"tick\". GameBoy is copyrighted by\r\n          Nintendo Co., LTD. Any reference to copyrighted material is\r\n          not presented for monetary gain, but for educational purposes\r\n          and higher learning.\r\n\r\nTerms\r\n-----\r\n\r\n GB = Original GameBoy\r\n GBP = GameBoy Pocket/GameBoy Light\r\n GBC = GameBoy Color\r\n SGB = Super GameBoy\r\n\r\n\r\nGame Boy Specs\r\n--------------\r\n\r\n CPU: 8-bit (Similar to the Z80 processor.)\r\n Main RAM: 8K Byte\r\n Video RAM: 8K Byte\r\n Screen Size 2.6\"\r\n Resolution: 160x144 (20x18 tiles)\r\n Max # of sprites: 40\r\n Max # sprites/line: 10\r\n Max sprite size: 8x16\r\n Min sprite size: 8x8\r\n Clock Speed: 4.194304 MHz (4.295454 SGB, 4.194/8.388MHz GBC)\r\n Horiz Sync: 9198 KHz (9420 KHz for SGB)\r\n Vert Sync: 59.73 Hz (61.17 Hz for SGB)\r\n Sound: 4 channels with stereo sound\r\n Power: DC6V 0.7W (DC3V 0.7W for GB Pocket)\r\n\r\n\r\nProcessor\r\n---------\r\n\r\n  The GameBoy uses a computer chip similar to an Intel 8080.\r\n It contains all of the instructions of an 8080 except there\r\n are no exchange instructions. In many ways the processor is\r\n more similar to the Zilog Z80 processor. Compared to the\r\n Z80, some instructions have been added and some have been\r\n taken away.\r\n\r\n The following are added instructions:\r\n\r\n  ADD  SP,nn             ;nn = signed byte\r\n  LDI  (HL),A            ;Write A to (HL) and increment HL\r\n  LDD  (HL),A            ;Write A to (HL) and decrement HL\r\n  LDI  A,(HL)            ;Write (HL) to A and increment HL\r\n  LDD  A,(HL)            ;Write (HL) to A and decrement HL\r\n  LD  A,($FF00+nn)\r\n  LD  A,($FF00+C)\r\n  LD  ($FF00+nn),A\r\n  LD  ($FF00+C),A\r\n  LD  (nnnn),SP\r\n  LD  HL,SP+nn           ;nn = signed byte\r\n  STOP                   ;Stop processor & screen until button press\r\n  SWAP r                 ;Swap high & low nibbles of r\r\n\r\n The following instructions have been removed:\r\n\r\n  Any command that uses the IX or IY registers.\r\n  All IN/OUT instructions.\r\n  All exchange instructions.\r\n  All commands prefixed by ED (except remapped RETI).\r\n  All conditional jumps/calls/rets on parity/overflow and sign flag.\r\n\r\n The following instructions have different opcodes:\r\n\r\n  LD  A,[nnnn]\r\n  LD  [nnnn],A\r\n  RETI\r\n\r\n\r\nGeneral Memory Map*                  Hardware Write Registers\r\n------------------                   ------------------------\r\n\r\n  Interrupt Enable Register\r\n --------------------------- FFFF\r\n  Internal RAM\r\n --------------------------- FF80\r\n  Empty but unusable for I/O\r\n --------------------------- FF4C\r\n  I/O ports\r\n --------------------------- FF00\r\n  Empty but unusable for I/O\r\n --------------------------- FEA0\r\n  Sprite Attrib Memory (OAM)\r\n --------------------------- FE00\r\n  Echo of 8kB Internal RAM\r\n --------------------------- E000\r\n  8kB Internal RAM\r\n --------------------------- C000       -------------------------\r\n  8kB switchable RAM bank              /      MBC1 ROM/RAM Select\r\n --------------------------- A000     /  ------------------------\r\n  8kB Video RAM                      /  /     RAM Bank Select\r\n --------------------------- 8000 --/  /  -----------------------\r\n  16kB switchable ROM bank   6000 ----/  /    ROM Bank Select\r\n --------------------------- 4000 ------/  ----------------------\r\n  16kB ROM bank #0           2000 --------/   RAM Bank enable\r\n --------------------------- 0000 -------------------------------\r\n\r\n * NOTE: b = bit, B = byte\r\n\r\n\r\nEcho of 8kB Internal RAM\r\n------------------------\r\n\r\n The addresses E000-FE00 appear to access the internal RAM\r\nthe same as C000-DE00. (i.e. If you write a byte to address\r\nE000 it will appear at C000 and E000. Similarly, writing a\r\nbyte to C000 will appear at C000 and E000.)\r\n\r\n\r\nUser I/O\r\n--------\r\n\r\n There are no empty spaces in the memory map for\r\nimplementing input ports except the switchable RAM bank\r\narea (not an option on the Super Smart Card since it's\r\nRAM bank is always enabled).\r\n\r\n An output only port may be implemented anywhere between\r\nA000-FDFF. If implemented in a RAM area care should be\r\ntaken to use an area of RAM not used for anything else.\r\n(FE00 and above can't be used because the CPU doesn't\r\ngenerate an external /WR for these locations.)\r\n\r\n If you have a cart with an MBC1, a ROM 4Mbit or smaller,\r\nand a RAM 8Kbyte or smaller (or no RAM) then you can use\r\npins 6 & 7 of the MBC1 for 2 digital output pins for\r\nwhatever purpose you wish. To use them you must first\r\nput the MBC1 into 4MbitROM/32KbyteRAM mode by writing\r\n01 to 6000. The two least significant bits you write\r\nto 4000 will then be output to these pins.\r\n\r\n\r\nReserved Memory Locations\r\n-------------------------\r\n\r\n0000       Restart $00 Address (RST $00 calls this address.)\r\n\r\n0008       Restart $08 Address (RST $08 calls this address.)\r\n\r\n0010       Restart $10 Address (RST $10 calls this address.)\r\n\r\n0018       Restart $18 Address (RST $18 calls this address.)\r\n\r\n0020       Restart $20 Address (RST $20 calls this address.)\r\n\r\n0028       Restart $28 Address (RST $28 calls this address.)\r\n\r\n0030       Restart $30 Address (RST $30 calls this address.)\r\n\r\n0038       Restart $38 Address (RST $38 calls this address.)\r\n\r\n0040       Vertical Blank Interrupt Start Address\r\n\r\n0048       LCDC Status Interrupt Start Address\r\n\r\n0050       Timer Overflow Interrupt Start Address\r\n\r\n0058       Serial Transfer Completion Interrupt Start Address\r\n\r\n0060       High-to-Low of P10-P13 Interrupt Start Address\r\n\r\nAn internal information area is located at 0100-014F in\r\neach cartridge. It contains the following values:\r\n\r\n0100-0103  This is the begin code execution point in a\r\n           cart. Usually there is a NOP and a JP\r\n           instruction here but not always.\r\n\r\n0104-0133  Scrolling Nintendo graphic:\r\n           CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D\r\n           00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99\r\n           BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E\r\n           ( PROGRAM WON'T RUN IF CHANGED!!!)\r\n\r\n0134-0142  Title of the game in UPPER CASE ASCII. If it\r\n           is less than 16 characters then the remaining\r\n           bytes are filled with 00's.\r\n\r\n0143       $80 = Color GB, $00 or other = not Color GB\r\n\r\n0144       Ascii hex digit, high nibble of licensee code (new).\r\n0145       Ascii hex digit, low nibble of licensee code (new).\r\n           (These are normally $00 if [$014B] <> $33.)\r\n\r\n0146       GB/SGB Indicator (00 = GameBoy, 03 = Super GameBoy functions)\r\n           (Super GameBoy functions won't work if <> $03.)\r\n\r\n0147       Cartridge type:\r\n           0 - ROM ONLY                12 - ROM+MBC3+RAM\r\n           1 - ROM+MBC1                13 - ROM+MBC3+RAM+BATT\r\n           2 - ROM+MBC1+RAM            19 - ROM+MBC5\r\n           3 - ROM+MBC1+RAM+BATT       1A - ROM+MBC5+RAM\r\n           5 - ROM+MBC2                1B - ROM+MBC5+RAM+BATT\r\n           6 - ROM+MBC2+BATTERY        1C - ROM+MBC5+RUMBLE\r\n           8 - ROM+RAM                 1D - ROM+MBC5+RUMBLE+SRAM\r\n           9 - ROM+RAM+BATTERY         1E - ROM+MBC5+RUMBLE+SRAM+BATT\r\n           B - ROM+MMM01               1F - Pocket Camera\r\n           C - ROM+MMM01+SRAM          FD - Bandai TAMA5\r\n           D - ROM+MMM01+SRAM+BATT     FE - Hudson HuC-3\r\n           F - ROM+MBC3+TIMER+BATT     FF - Hudson HuC-1\r\n          10 - ROM+MBC3+TIMER+RAM+BATT\r\n          11 - ROM+MBC3\r\n\r\n0148       ROM size:\r\n             0 - 256Kbit =  32KByte =   2 banks\r\n             1 - 512Kbit =  64KByte =   4 banks\r\n             2 -   1Mbit = 128KByte =   8 banks\r\n             3 -   2Mbit = 256KByte =  16 banks\r\n             4 -   4Mbit = 512KByte =  32 banks\r\n             5 -   8Mbit =   1MByte =  64 banks\r\n             6 -  16Mbit =   2MByte = 128 banks\r\n           $52 -   9Mbit = 1.1MByte =  72 banks\r\n           $53 -  10Mbit = 1.2MByte =  80 banks\r\n           $54 -  12Mbit = 1.5MByte =  96 banks\r\n\r\n0149       RAM size:\r\n           0 - None\r\n           1 -  16kBit =  2kB = 1 bank\r\n           2 -  64kBit =  8kB = 1 bank\r\n           3 - 256kBit = 32kB = 4 banks\r\n           4 -   1MBit =128kB =16 banks\r\n\r\n014A       Destination code:\r\n           0 - Japanese\r\n           1 - Non-Japanese\r\n\r\n014B       Licensee code (old):\r\n           33 - Check 0144/0145 for Licensee code.\r\n           79 - Accolade\r\n           A4 - Konami\r\n           (Super GameBoy function won't work if <> $33.)\r\n\r\n014C       Mask ROM Version number (Usually $00)\r\n\r\n014D       Complement check\r\n           (PROGRAM WON'T RUN ON GB IF NOT CORRECT!!!)\r\n           (It will run on Super GB, however, if incorrect.)\r\n\r\n014E-014F  Checksum (higher byte first) produced by\r\n           adding all bytes of a cartridge except for two\r\n           checksum bytes and taking two lower bytes of\r\n           the result. (GameBoy ignores this value.)\r\n\r\n\r\nCartridge Types\r\n---------------\r\n\r\nThe following define the byte at cart location 0147:\r\n\r\n ROM ONLY\r\n  This is a 32kB (256kb) ROM and occupies 0000-7FFF.\r\n\r\n MBC1 (Memory Bank Controller 1)\r\n   MBC1 has two different maximum memory modes:\r\n  16Mbit ROM/8KByte RAM  or  4Mbit ROM/32KByte RAM.\r\n\r\n   The MBC1 defaults to 16Mbit ROM/8KByte RAM mode\r\n  on power up. Writing a value (XXXXXXXS - X = Don't\r\n  care, S = Memory model select) into 6000-7FFF area\r\n  will select the memory model to use. S = 0 selects\r\n  16/8 mode. S = 1 selects 4/32 mode.\r\n\r\n   Writing a value (XXXBBBBB - X = Don't cares, B =\r\n  bank select bits) into 2000-3FFF area will select an\r\n  appropriate ROM bank at 4000-7FFF. Values of 0 and 1\r\n  do the same thing and point to ROM bank 1. Rom bank 0\r\n  is not accessible from 4000-7FFF and can only be read\r\n  from 0000-3FFF.\r\n\r\n  If memory model is set to 4/32:\r\n    Writing a value (XXXXXXBB - X = Don't care, B =\r\n   bank select bits) into 4000-5FFF area will select an\r\n   appropriate RAM bank at A000-C000. Before you can\r\n   read or write to a RAM bank you have to enable it by\r\n   writing a XXXX1010 into 0000-1FFF area*. To disable\r\n   RAM bank operations write any value but XXXX1010\r\n   into 0000-1FFF area. Disabling a RAM bank probably\r\n   protects that bank from false writes during power\r\n   down of the GameBoy. (NOTE: Nintendo suggests values\r\n   $0A to enable and $00 to disable RAM bank!!)\r\n\r\n  If memory model is set to 16/8 mode:\r\n    Writing a value (XXXXXXBB - X = Don't care, B =\r\n   bank select bits) into 4000-5FFF area will set the\r\n   two most significant ROM address lines.\r\n\r\n  * NOTE: The Super Smart Card doesn't require this\r\n   operation because it's RAM bank is ALWAYS enabled.\r\n   Include this operation anyway to allow your code\r\n   to work with both.\r\n\r\n MBC2 (Memory Bank Controller 2):\r\n   This memory controller works much like the MBC1\r\n  controller with the following exceptions:\r\n\r\n   MBC2 will work with ROM sizes up to 2Mbit.\r\n\r\n   Writing a value (XXXXBBBB - X = Don't cares, B =\r\n  bank select bits) into 2000-3FFF area will select an\r\n  appropriate ROM bank at 4000-7FFF.\r\n\r\n   RAM switching is not provided. Unlike the MBC1 which\r\n  uses external RAM, MBC2 has 512 x 4 bits of RAM which\r\n  is in the controller itself. It still requires an\r\n  external battery to save data during power-off though.\r\n\r\n   The least significant bit of the upper address byte\r\n  must be zero to enable/disable cart RAM. For example\r\n  the following addresses can be used to enable/disable\r\n  cart RAM:\r\n  0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.\r\n  The suggested address range to use for MBC2 ram\r\n  enable/disable is 0000-00FF.\r\n\r\n   The least significant bit of the upper address byte\r\n  must be one to select a ROM bank. For example the\r\n  following addresses can be used to select a ROM bank:\r\n  2100-21FF, 2300-23FF, 2500-25FF, ..., 3F00-3FFF.\r\n  The suggested address range to use for MBC2 rom\r\n  bank selection is 2100-21FF.\r\n\r\n MBC3 (Memory Bank Controller 3):\r\n   This controller is similar to MBC1 except it accesses\r\n  all 16mbits of ROM without requiring any writes to the\r\n  4000-5FFF area.\r\n    Writing a value (XBBBBBBB - X = Don't care, B =\r\n  bank select bits) into 2000-3FFF area will select an\r\n  appropriate ROM bank at 4000-7FFF.\r\n\r\n   Also, this MBC has a built-in battery-backed Real\r\n  Time Clock (RTC) not found in any other MBC. Some\r\n  MBC3 carts do not support it (WarioLand II non-color\r\n  version) but some do (Harvest Moon/Japanese version.)\r\n\r\n MBC5 (Memory Bank Controller 5):\r\n   This controller is the first MBC that is guaranteed\r\n  to run in GameBoy Color double-speed mode but it\r\n  appears the other MBC's run fine in GBC double-speed\r\n  mode as well.\r\n\r\n   It is similar to the MBC3 (but no RTC) but can\r\n  access up to 64mbits of ROM and up to 1mbit of RAM.\r\n  The lower 8 bits of the 9-bit rom bank select is\r\n  written to the 2000-2FFF area while the upper bit\r\n  is written to the least significant bit of the\r\n  3000-3FFF area.\r\n\r\n    Writing a value (XXXXBBBB - X = Don't care, B =\r\n  bank select bits) into 4000-5FFF area will select an\r\n  appropriate RAM bank at A000-BFFF if the cart\r\n  contains RAM. Ram sizes are 64kbit,256kbit, & 1mbit.\r\n\r\n   Also, this is the first MBC that allows rom bank 0\r\n  to appear in the 4000-7FFF range by writing $000\r\n  to the rom bank select.\r\n\r\n Rumble Carts:\r\n   Rumble carts use an MBC5 memory bank controller.\r\n  Rumble carts can only have up to 256kbits of RAM.\r\n  The highest RAM address line that allows 1mbit of\r\n  RAM on MBC5 non-rumble carts is used as the motor\r\n  on/off for the rumble cart.\r\n\r\n    Writing a value (XXXXMBBB - X = Don't care, M =\r\n  motor, B = bank select bits) into 4000-5FFF area\r\n  will select an appropriate RAM bank at A000-BFFF\r\n  if the cart contains RAM. RAM sizes are 64kbit or\r\n  256kbits. To turn the rumble motor on set M = 1,\r\n  M = 0 turns it off.\r\n\r\n HuC1 (Memory Bank / Infrared Controller):\r\n   This controller made by Hudson Soft appears to be\r\n  very similar to an MBC1 with the main difference\r\n  being that it supports infrared LED input / output.\r\n  The Japanese cart \"Fighting Phoenix\" (internal cart\r\n  name: SUPER B DAMAN) is known to contain this chip.\r\n\r\n\r\n\r\nPower Up Sequence\r\n-----------------\r\n\r\n  When the GameBoy is powered up, a 256 byte program\r\n starting at memory location 0 is executed. This program\r\n is located in a ROM inside the GameBoy. The first thing\r\n the program does is read the cartridge locations from\r\n $104 to $133 and place this graphic of a Nintendo logo\r\n on the screen at the top. This image is then scrolled\r\n until it is in the middle of the screen. Two musical\r\n notes are then played on the internal speaker. Again,\r\n the cartridge locations $104 to $133 are read but this\r\n time they are compared with a table in the internal rom.\r\n If any byte fails to compare, then the GameBoy stops\r\n comparing bytes and simply halts all operations.\r\n\r\n GB & GB Pocket:\r\n      Next, the GameBoy starts adding all of the bytes\r\n      in the cartridge from $134 to $14d. A value of 25\r\n      decimal is added to this total. If the least\r\n      significant byte of the result is a not a zero,\r\n      then the GameBoy will stop doing anything.\r\n\r\n Super GB:\r\n      Even though the GB & GBP check the memory locations\r\n      from $134 to $14d, the SGB doesn't.\r\n\r\n  If the above checks pass then the internal ROM is\r\n disabled and cartridge program execution begins at\r\n location $100 with the following register values:\r\n\r\n   AF=$01-GB/SGB, $FF-GBP, $11-GBC\r\n   F =$B0\r\n   BC=$0013\r\n   DE=$00D8\r\n   HL=$014D\r\n   Stack Pointer=$FFFE\r\n   [$FF05] = $00   ; TIMA\r\n   [$FF06] = $00   ; TMA\r\n   [$FF07] = $00   ; TAC\r\n   [$FF10] = $80   ; NR10\r\n   [$FF11] = $BF   ; NR11\r\n   [$FF12] = $F3   ; NR12\r\n   [$FF14] = $BF   ; NR14\r\n   [$FF16] = $3F   ; NR21\r\n   [$FF17] = $00   ; NR22\r\n   [$FF19] = $BF   ; NR24\r\n   [$FF1A] = $7F   ; NR30\r\n   [$FF1B] = $FF   ; NR31\r\n   [$FF1C] = $9F   ; NR32\r\n   [$FF1E] = $BF   ; NR33\r\n   [$FF20] = $FF   ; NR41\r\n   [$FF21] = $00   ; NR42\r\n   [$FF22] = $00   ; NR43\r\n   [$FF23] = $BF   ; NR30\r\n   [$FF24] = $77   ; NR50\r\n   [$FF25] = $F3   ; NR51\r\n   [$FF26] = $F1-GB, $F0-SGB ; NR52\r\n   [$FF40] = $91   ; LCDC\r\n   [$FF42] = $00   ; SCY\r\n   [$FF43] = $00   ; SCX\r\n   [$FF45] = $00   ; LYC\r\n   [$FF47] = $FC   ; BGP\r\n   [$FF48] = $FF   ; OBP0\r\n   [$FF49] = $FF   ; OBP1\r\n   [$FF4A] = $00   ; WY\r\n   [$FF4B] = $00   ; WX\r\n   [$FFFF] = $00   ; IE\r\n\r\n It is not a good idea to assume the above values\r\nwill always exist. A later version GameBoy could\r\ncontain different values than these at reset.\r\nAlways set these registers on reset rather than\r\nassume they are as above.\r\n\r\n Please note that GameBoy internal RAM on power up\r\ncontains random data. All of the GameBoy emulators\r\ntend to set all RAM to value $00 on entry.\r\n\r\n Cart RAM the first time it is accessed on a real\r\nGameBoy contains random data. It will only contain\r\nknown data if the GameBoy code initializes it to\r\nsome value.\r\n\r\nStop Mode\r\n---------\r\n\r\n  The STOP command halts the GameBoy processor\r\n and screen until any button is pressed. The GB\r\n and GBP screen goes white with a single dark\r\n horizontal line. The GBC screen goes black.\r\n\r\n\r\nLow-Power Mode\r\n--------------\r\n\r\n  It is recommended that the HALT instruction be used\r\n whenever possible to reduce power consumption & extend\r\n the life of the batteries. This command stops the\r\n system clock reducing the power consumption of both\r\n the CPU and ROM.\r\n\r\n  The CPU will remain suspended until an interrupt\r\n occurs at which point the interrupt is serviced and\r\n then the instruction immediately following the HALT\r\n is executed. If interrupts are disabled (DI) then\r\n halt doesn't suspend operation but it does cause\r\n the program counter to stop counting for one\r\n instruction on the GB,GBP, and SGB as mentioned below.\r\n\r\n  Depending on how much CPU time is required by a game,\r\n the HALT instruction can extend battery life anywhere\r\n from 5 to 50% or possibly more.\r\n\r\n WARNING: The instruction immediately following the\r\n  HALT instruction is \"skipped\" when interrupts are\r\n  disabled (DI) on the GB,GBP, and SGB. As a result,\r\n  always put a NOP after the HALT instruction. This\r\n  instruction skipping doesn't occur when interrupts\r\n  are enabled (EI).\r\n   This \"skipping\" does not seem to occur on the\r\n  GameBoy Color even in regular GB mode. ($143=$00)\r\n\r\n EXAMPLES from Martin Korth who documented this problem:\r\n  (assuming interrupts disabled for all examples)\r\n\r\n1) This code causes the 'a' register to be incremented TWICE.\r\n      76          halt\r\n      3C          inc  a\r\n\r\n2) The next example is a bit more difficult. The following code\r\n      76          halt\r\n      FA 34 12    ld   a,(1234)\r\n\r\n   is effectively executed as\r\n\r\n      76          halt\r\n      FA FA 34    ld   a,(34FA)\r\n      12          ld   (de),a\r\n\r\n3) Finally an interesting side effect\r\n      76          halt\r\n      76          halt\r\n\r\n    This combination hangs the cpu.\r\n   The first HALT causes the second HALT to be repeated, which\r\n   therefore causes the following command (=itself) to be\r\n   repeated - again and again.\r\n   Placing a NOP between the two halts would cause the NOP to\r\n   be repeated once, the second HALT wouldn't lock the cpu.\r\n\r\n  Below is suggested code for GameBoy programs:\r\n\r\n  ; **** Main Game Loop ****\r\n  Main:\r\n        halt                    ; stop system clock\r\n                                ; return from halt when interrupted\r\n        nop                     ; (See WARNING above.)\r\n\r\n        ld      a,(VblnkFlag)\r\n        or      a               ; V-Blank interrupt ?\r\n        jr      z,Main          ; No, some other interrupt\r\n\r\n        xor     a\r\n        ld      (VblnkFlag),a   ; Clear V-Blank flag\r\n\r\n        call    Controls        ; button inputs\r\n        call    Game            ; game operation\r\n\r\n        jr      Main\r\n\r\n  ; **** V-Blank Interrupt Routine ****\r\n  Vblnk:\r\n        push    af\r\n        push    bc\r\n        push    de\r\n        push    hl\r\n\r\n        call    SpriteDma       ; Do sprite updates\r\n\r\n        ld      a,1\r\n        ld      (VblnkFlag),a\r\n\r\n        pop     hl\r\n        pop     de\r\n        pop     bc\r\n        pop     af\r\n        reti\r\n\r\n\r\nVideo\r\n-----\r\n\r\n  The main GameBoy screen buffer (background) consists\r\n of 256x256 pixels or 32x32 tiles (8x8 pixels each). Only\r\n 160x144 pixels can be displayed on the screen. Registers\r\n SCROLLX and SCROLLY hold the coordinates of background to\r\n be displayed in the left upper corner of the screen.\r\n Background wraps around the screen (i.e. when part of it\r\n goes off the screen, it appears on the opposite side.)\r\n\r\n  An area of VRAM known as Background Tile Map contains\r\n the numbers of tiles to be displayed. It is organized as\r\n 32 rows of 32 bytes each. Each byte contains a number of\r\n a tile to be displayed. Tile patterns are taken from the\r\n Tile Data Table located either at $8000-8FFF or\r\n $8800-97FF. In the first case, patterns are numbered with\r\n unsigned numbers from 0 to 255 (i.e. pattern #0 lies at\r\n address $8000). In the second case, patterns have signed\r\n numbers from -128 to 127 (i.e. pattern #0 lies at address\r\n $9000). The Tile Data Table address for the background\r\n can be selected by setting the LCDC register.\r\n\r\n  There are two different Background Tile Maps. One is\r\n located from $9800-9Bff. The other from $9C00-9FFF.\r\n Only one of these can be viewed at any one time. The\r\n currently displayed background can be selected by\r\n setting the LCDC register.\r\n\r\n  Besides background, there is also a \"window\" overlaying\r\n the background. The window is not scrollable i.e. it is\r\n always displayed starting from its left upper corner. The\r\n location of a window on the screen can be adjusted via\r\n WNDPOSX and WNDPOSY registers. Screen coordinates of the\r\n top left corner of a window are WNDPOSX-7,WNDPOSY. The\r\n tile numbers for the window are stored in the Tile Data\r\n Table. None of the windows tiles are ever transparent.\r\n Both the Background and the window share the same Tile\r\n Data Table.\r\n\r\n  Both background and window can be disabled or enabled\r\n separately via bits in the LCDC register.\r\n\r\n  If the window is used and a scan line interrupt disables\r\n it (either by writing to LCDC or by setting WX > 166)\r\n and a scan line interrupt a little later on enables it\r\n then the window will resume appearing on the screen at the\r\n exact position of the window where it left off earlier.\r\n This way, even if there are only 16 lines of useful graphics\r\n in the window, you could display the first 8 lines at the\r\n top of the screen and the next 8 lines at the bottom if\r\n you wanted to do so.\r\n\r\n  WX may be changed during a scan line interrupt (to either\r\n cause a graphic distortion effect or to disable the window\r\n (WX>166) ) but changes to WY are not dynamic and won't\r\n be noticed until the next screen redraw.\r\n\r\n  The tile images are stored in the Tile Pattern Tables.\r\n Each 8x8 image occupies 16 bytes, where each 2 bytes\r\n represent a line:\r\n\r\n  Tile:                                     Image:\r\n\r\n  .33333..                     .33333.. -> 01111100 -> $7C\r\n  22...22.                                 01111100 -> $7C\r\n  11...11.                     22...22. -> 00000000 -> $00\r\n  2222222. <-- digits                      11000110 -> $C6\r\n  33...33.     represent       11...11. -> 11000110 -> $C6\r\n  22...22.     color                       00000000 -> $00\r\n  11...11.     numbers         2222222. -> 00000000 -> $00\r\n  ........                                 11111110 -> $FE\r\n                               33...33. -> 11000110 -> $C6\r\n                                           11000110 -> $C6\r\n                               22...22. -> 00000000 -> $00\r\n                                           11000110 -> $C6\r\n                               11...11. -> 11000110 -> $C6\r\n                                           00000000 -> $00\r\n                               ........ -> 00000000 -> $00\r\n                                           00000000 -> $00\r\n\r\n  As it was said before, there are two Tile Pattern Tables\r\n at $8000-8FFF and at $8800-97FF. The first one can be used\r\n for sprites, the background, and the window display. Its\r\n tiles are numbered from 0 to 255. The second table can be\r\n used for the background and the window display and its tiles\r\n are numbered from -128 to 127.\r\n\r\n\r\nSprites\r\n------\r\n\r\n  GameBoy video controller can display up to 40 sprites\r\n either in 8x8 or in 8x16 pixels. Because of a limitation\r\n of hardware, only ten sprites can be displayed per scan\r\n line. Sprite patterns have the same format as tiles, but\r\n they are taken from the Sprite Pattern Table located at\r\n $8000-8FFF and have unsigned numbering. Sprite\r\n attributes reside in the Sprite Attribute Table (OAM\r\n - Object Attribute Memory) at $FE00-FE9F. OAM is divided\r\n into 40 4-byte blocks each of which corresponds to a sprite.\r\n\r\n  In 8x16 sprite mode, the least significant bit of the\r\n sprite pattern number is ignored and treated as 0.\r\n\r\n  When sprites with different x coordinate values overlap,\r\n the one with the smaller x coordinate (closer to the left)\r\n will have priority and appear above any others.\r\n\r\n  When sprites with the same x coordinate values overlap,\r\n they have priority according to table ordering. (i.e.\r\n $FE00 - highest, $FE04 - next highest, etc.)\r\n\r\n  Please note that Sprite X=0, Y=0 hides a sprite. To\r\n display a sprite use the following formulas:\r\n\r\n SpriteScreenPositionX(Upper left corner of sprite) = SpriteX - 8\r\n SpriteScreenPositionY(Upper left corner of sprite) = SpriteY - 16\r\n\r\n  To display a sprite in the upper left corner of the\r\n screen set sprite X=8, Y=16.\r\n\r\n  Only 10 sprites can be displayed on any one line.\r\n When this limit is exceeded, the lower priority sprites\r\n (priorities listed above) won't be displayed. To keep\r\n unused sprites from affecting onscreen sprites set their\r\n Y coordinate to Y=0 or Y=>144+16. Just setting the X\r\n coordinate to X=0 or X=>160+8 on a sprite will hide it\r\n but it will still affect other sprites sharing the same\r\n lines.\r\n\r\n Blocks have the following\r\n format:\r\n\r\n  Byte0  Y position on the screen\r\n  Byte1  X position on the screen\r\n  Byte2  Pattern number 0-255 (Unlike some tile\r\n         numbers, sprite pattern numbers are unsigned.\r\n         LSB is ignored (treated as 0) in 8x16 mode.)\r\n  Byte3  Flags:\r\n\r\n         Bit7  Priority\r\n               If this bit is set to 0, sprite is displayed\r\n               on top of background & window. If this bit\r\n               is set to 1, then sprite will be hidden behind\r\n               colors 1, 2, and 3 of the background & window.\r\n               (Sprite only prevails over color 0 of BG & win.)\r\n         Bit6  Y flip\r\n               Sprite pattern is flipped vertically if\r\n               this bit is set to 1.\r\n         Bit5  X flip\r\n               Sprite pattern is flipped horizontally if\r\n               this bit is set to 1.\r\n         Bit4  Palette number\r\n               Sprite colors are taken from OBJ1PAL if\r\n               this bit is set to 1 and from OBJ0PAL\r\n               otherwise.\r\n\r\n\r\nSprite RAM Bug\r\n--------------\r\n\r\n  There is a flaw in the GameBoy hardware that causes\r\n trash to be written to OAM RAM if the following commands\r\n are used while their 16-bit content is in the range\r\n of $FE00 to $FEFF:\r\n\r\n  inc xx     (xx = bc,de, or hl)\r\n  dec xx\r\n\r\n  ldi a,(hl)\r\n  ldd a,(hl)\r\n\r\n  ldi (hl),a\r\n  ldd (hl),a\r\n\r\n  Only sprites 1 & 2 ($FE00 & $FE04) are not affected\r\n by these instructions.\r\n\r\n\r\nSound\r\n-----\r\n\r\n  There are two sound channels connected to the output\r\n terminals SO1 and SO2. There is also a input terminal Vin\r\n connected to the cartridge. It can be routed to either of\r\n both output terminals. GameBoy circuitry allows producing\r\n sound in four different ways:\r\n\r\n   Quadrangular wave patterns with sweep and envelope functions.\r\n   Quadrangular wave patterns with envelope functions.\r\n   Voluntary wave patterns from wave RAM.\r\n   White noise with an envelope function.\r\n\r\n  These four sounds can be controlled independantly and\r\n then mixed separately for each of the output terminals.\r\n\r\n  Sound registers may be set at all times while producing\r\n sound.\r\n\r\n  When setting the initial value of the envelope and\r\n restarting the length counter, set the initial flag to 1\r\n and initialize the data.\r\n\r\n  Under the following situations the Sound ON flag is\r\n reset and the sound output stops:\r\n\r\n  1. When the sound output is stopped by the length counter.\r\n  2. When overflow occurs at the addition mode while sweep\r\n     is operating at sound 1.\r\n\r\n  When the Sound OFF flag for sound 3 (bit 7 of NR30) is\r\n set at 0, the cancellation of the OFF mode must be done\r\n by setting the sound OFF flag to 1. By initializing\r\n sound 3, it starts it's function.\r\n\r\n  When the All Sound OFF flag (bit 7 of NR52) is set to 0,\r\n the mode registers for sounds 1,2,3, and 4 are reset and\r\n the sound output stops. (NOTE: The setting of each sounds\r\n mode register must be done after the All Sound OFF mode\r\n is cancelled. During the All Sound OFF mode, each sound\r\n mode register cannot be set.)\r\n\r\n  NOTE: DURING THE ALL SOUND OFF MODE, GB POWER CONSUMPTION\r\n DROPS BY 16% OR MORE! WHILE YOUR PROGRAMS AREN'T USING\r\n SOUND THEN SET THE ALL SOUND OFF FLAG TO 0. IT DEFAULTS\r\n TO 1 ON RESET.\r\n\r\n  These tend to be the two most important equations in\r\n converting between Hertz and GB frequency registers:\r\n (Sounds will have a 2.4% higher frequency on Super GB.)\r\n\r\n     gb = 2048 - (131072 / Hz)\r\n\r\n     Hz  = 131072 / (2048 - gb)\r\n\r\n\r\nTimer\r\n-----\r\n\r\n  Sometimes it's useful to have a timer that interrupts at\r\n regular intervals for routines that require periodic or\r\n percise updates. The timer in the GameBoy has a selectable\r\n frequency of 4096, 16384, 65536, or 262144 Hertz. This\r\n frequency increments the Timer Counter (TIMA). When it\r\n overflows, it generates an interrupt. It is then loaded\r\n with the contents of Timer Modulo (TMA). The following\r\n are examples:\r\n\r\n ;This interval timer interrupts 4096 times per second\r\n\r\n     ld  a,-1\r\n     ld  ($FF06),a     ;Set TMA to divide clock by 1\r\n     ld  a,4\r\n     ld  ($FF07),a     ;Set clock to 4096 Hertz\r\n\r\n ;This interval timer interrupts 65536 times per second\r\n\r\n     ld  a,-4\r\n     ld  ($FF06),a     ;Set TMA to divide clock by 4\r\n     ld  a,5\r\n     ld  ($FF07),a     ;Set clock to 262144 Hertz\r\n\r\n\r\nSerial I/O\r\n----------\r\n\r\n  The serial I/O port on the Gameboy is a very simple setup\r\n and is crude compared to standard RS-232 (IBM-PC) or RS-485\r\n (Macintosh) serial ports. There are no start or stop bits\r\n so the programmer must be more creative when using this port.\r\n\r\n  During a transfer, a byte is shifted in at the same time\r\n that a byte is shifted out. The rate of the shift is deter-\r\n mined by whether the clock source is internal or external.\r\n If internal, the bits are shifted out at a rate of 8192Hz\r\n (122 microseconds) per bit. The most significant bit is\r\n shifted in and out first.\r\n\r\n  When the internal clock is selected, it drives the clock\r\n pin on the game link port and it stays high when not used.\r\n During a transfer it will go low eight times to clock\r\n in/out each bit.\r\n\r\n  A programmer initates a serial transfer by setting bit 7\r\n of $FF02. This bit may be read and is automatically set\r\n to 0 at the completion of transfer. After this bit is set,\r\n an interrupt will then occur eight bit clocks later if the\r\n serial interrupt is enabled.\r\n  If internal clock is selected and serial interrupt is\r\n enabled, this interrupt occurs 122*8 microseconds later.\r\n  If external clock is selected and serial interrupt is\r\n enabled, an interrupt will occur eight bit clocks later.\r\n\r\n  Initiating a serial transfer with external clock will\r\n wait forever if no external clock is present. This allows\r\n a certain amount of synchronization with each serial port.\r\n\r\n  The state of the last bit shifted out determines the\r\n state of the output line until another transfer takes\r\n place.\r\n\r\n  If a serial transfer with internal clock is performed\r\n and no external GameBoy is present, a value of $FF will\r\n be received in the transfer.\r\n\r\n  The following code causes $75 to be shifted out the\r\n serial port and a byte to be shifted into $FF01:\r\n\r\n    ld   a,$75\r\n    ld  ($FF01),a\r\n    ld   a,$81\r\n    ld  ($FF02),a\r\n\r\n\r\nInterrupt Procedure\r\n-------------------\r\n\r\n  The IME (interrupt master enable) flag is reset by DI and\r\n prohibits all interrupts. It is set by EI and acknowledges\r\n the interrupt setting by the IE register.\r\n\r\n 1. When an interrupt is generated, the IF flag will be set.\r\n 2. If the IME flag is set & the corresponding IE flag is\r\n    set, the following 3 steps are performed.\r\n 3. Reset the IME flag and prevent all interrupts.\r\n 4. The PC (program counter) is pushed onto the stack.\r\n 5. Jump to the starting address of the interrupt.\r\n\r\n  Resetting of the IF register, which was the cause of the\r\n interrupt, is done by hardware.\r\n\r\n  During the interrupt, pushing of registers to be used\r\n should be performed by the interrupt routine.\r\n\r\n  Once the interrupt service is in progress, all the\r\n interrupts will be prohibited. However, if the IME flag\r\n and the IE flag are controlled, a number of interrupt\r\n services can be made possible by nesting.\r\n\r\n  Return from an interrupt routine can be performed by\r\n either RETI or RET instruction.\r\n\r\n  The RETI instruction enables interrupts after doing a\r\n return operation.\r\n\r\n  If a RET is used as the final instruction in an interrupt\r\n routine, interrupts will remain disabled unless a EI was\r\n used in the interrupt routine or is used at a later time.\r\n\r\n  The interrupt will be acknowledged during opcode fetch\r\n period of each instruction.\r\n\r\n\r\nInterrupt Descriptions\r\n----------------------\r\n\r\n  The following interrupts only occur if they have been\r\n enabled in the Interrupt Enable register ($FFFF) and\r\n if the interrupts have actually been enabled using the\r\n EI instruction.\r\n\r\n  V-Blank -\r\n\r\n   The V-Blank interrupt occurs ~59.7 times a second\r\n   on a regular GB and ~61.1 times a second on a Super\r\n   GB (SGB). This interrupt occurs at the beginning of\r\n   the V-Blank period. During this period video hardware\r\n   is not using video ram so it may be freely accessed.\r\n   This period lasts approximately 1.1 milliseconds.\r\n\r\n  LCDC Status -\r\n\r\n   There are various reasons for this interrupt to occur\r\n   as described by the STAT register ($FF40). One very\r\n   popular reason is to indicate to the user when the\r\n   video hardware is about to redraw a given LCD line.\r\n   This can be useful for dynamically controlling the SCX/\r\n   SCY registers ($FF43/$FF42) to perform special video\r\n   effects.\r\n\r\n  Timer Overflow -\r\n\r\n   This interrupt occurs when the TIMA register ($FF05)\r\n   changes from $FF to $00.\r\n\r\n  Serial Transfer Completion -\r\n\r\n   This interrupt occurs when a serial transfer has\r\n   completed on the game link port.\r\n\r\n  High-to-Low of P10-P13 -\r\n\r\n   This interrupt occurs on a transition of any of the\r\n   keypad input lines from high to low. Due to the fact\r\n   that keypad \"bounce\"* is virtually always present,\r\n   software should expect this interrupt to occur one\r\n   or more times for every button press and one or more\r\n   times for every button release.\r\n\r\n   * - Bounce tends to be a side effect of any button\r\n      making or breaking a connection. During these\r\n      periods, it is very common for a small amount of\r\n      oscillation between high & low states to take place.\r\n\r\nI/O Registers\r\n-------------\r\n\r\nFF00\r\n   Name     - P1\r\n   Contents - Register for reading joy pad info\r\n              and determining system type.    (R/W)\r\n\r\n           Bit 7 - Not used\r\n           Bit 6 - Not used\r\n           Bit 5 - P15 out port\r\n           Bit 4 - P14 out port\r\n           Bit 3 - P13 in port\r\n           Bit 2 - P12 in port\r\n           Bit 1 - P11 in port\r\n           Bit 0 - P10 in port\r\n\r\n         This is the matrix layout for register $FF00:\r\n\r\n\r\n                 P14        P15\r\n                  |          |\r\n        P10-------O-Right----O-A\r\n                  |          |\r\n        P11-------O-Left-----O-B\r\n                  |          |\r\n        P12-------O-Up-------O-Select\r\n                  |          |\r\n        P13-------O-Down-----O-Start\r\n                  |          |\r\n\r\n       Example code:\r\n\r\n          Game: Ms. Pacman\r\n          Address: $3b1\r\n\r\n        LD A,$20       <- bit 5 = $20\r\n        LD ($FF00),A   <- select P14 by setting it low\r\n        LD A,($FF00)\r\n        LD A,($FF00)   <- wait a few cycles\r\n        CPL            <- complement A\r\n        AND $0F        <- get only first 4 bits\r\n        SWAP A         <- swap it\r\n        LD B,A         <- store A in B\r\n        LD A,$10\r\n        LD ($FF00),A   <- select P15 by setting it low\r\n        LD A,($FF00)\r\n        LD A,($FF00)\r\n        LD A,($FF00)\r\n        LD A,($FF00)\r\n        LD A,($FF00)\r\n        LD A,($FF00)   <- Wait a few MORE cycles\r\n        CPL            <- complement (invert)\r\n        AND $0F        <- get first 4 bits\r\n        OR B           <- put A and B together\r\n\r\n        LD B,A         <- store A in D\r\n        LD A,($FF8B)   <- read old joy data from ram\r\n        XOR B          <- toggle w/current button bit\r\n        AND B          <- get current button bit back\r\n        LD ($FF8C),A   <- save in new Joydata storage\r\n        LD A,B         <- put original value in A\r\n        LD ($FF8B),A   <- store it as old joy data\r\n\r\n\r\n        LD A,$30       <- deselect P14 and P15\r\n        LD ($FF00),A   <- RESET Joypad\r\n        RET            <- Return from Subroutine\r\n\r\n          The button values using the above method are such:\r\n          $80 - Start             $8 - Down\r\n          $40 - Select            $4 - Up\r\n          $20 - B                 $2 - Left\r\n          $10 - A                 $1 - Right\r\n\r\n          Let's say we held down A, Start, and Up.\r\n          The value returned in accumulator A would be $94\r\n\r\n\r\nFF01\r\n   Name     - SB\r\n   Contents - Serial transfer data (R/W)\r\n\r\n              8 Bits of data to be read/written\r\n\r\nFF02\r\n   Name     - SC\r\n   Contents - SIO control  (R/W)\r\n\r\n              Bit 7 - Transfer Start Flag\r\n                      0: Non transfer\r\n                      1: Start transfer\r\n\r\n              Bit 0 - Shift Clock\r\n                      0: External Clock (500KHz Max.)\r\n                      1: Internal Clock (8192Hz)\r\n\r\n               Transfer is initiated by setting the\r\n              Transfer Start Flag. This bit may be read\r\n              and is automatically set to 0 at the end of\r\n              Transfer.\r\n\r\n               Transmitting and receiving serial data is\r\n              done simultaneously. The received data is\r\n              automatically stored in SB.\r\n\r\nFF04\r\n   Name     - DIV\r\n   Contents - Divider Register (R/W)\r\n\r\n              This register is incremented 16384 (~16779\r\n              on SGB) times a second. Writing any value\r\n              sets it to $00.\r\nFF05\r\n   Name     - TIMA\r\n   Contents - Timer counter (R/W)\r\n\r\n              This timer is incremented by a clock frequency\r\n              specified by the TAC register ($FF07). The timer\r\n              generates an interrupt when it overflows.\r\n\r\nFF06\r\n   Name     - TMA\r\n   Contents - Timer Modulo (R/W)\r\n\r\n              When the TIMA overflows, this data will be loaded.\r\n\r\nFF07\r\n   Name     - TAC\r\n   Contents - Timer Control (R/W)\r\n\r\n              Bit 2 - Timer Stop\r\n                      0: Stop Timer\r\n                      1: Start Timer\r\n\r\n              Bits 1+0 - Input Clock Select\r\n                         00: 4.096 KHz    (~4.194 KHz SGB)\r\n                         01: 262.144 KHz  (~268.4 KHz SGB)\r\n                         10: 65.536 KHz   (~67.11 KHz SGB)\r\n                         11: 16.384 KHz   (~16.78 KHz SGB)\r\n\r\nFF0F\r\n   Name     - IF\r\n   Contents - Interrupt Flag (R/W)\r\n\r\n              Bit 4: Transition from High to Low of Pin number P10-P13\r\n              Bit 3: Serial I/O transfer complete\r\n              Bit 2: Timer Overflow\r\n              Bit 1: LCDC (see STAT)\r\n              Bit 0: V-Blank\r\n\r\n   The priority and jump address for the above 5 interrupts are:\r\n\r\n    Interrupt        Priority        Start Address\r\n\r\n    V-Blank             1              $0040\r\n    LCDC Status         2              $0048 - Modes 0, 1, 2\r\n                                               LYC=LY coincide (selectable)\r\n    Timer Overflow      3              $0050\r\n    Serial Transfer     4              $0058 - when transfer is complete\r\n    Hi-Lo of P10-P13    5              $0060\r\n\r\n    * When more than 1 interrupts occur at the same time\r\n      only the interrupt with the highest priority can be\r\n      acknowledged. When an interrupt is used a '0' should\r\n      be stored in the IF register before the IE register\r\n      is set.\r\n\r\n\r\nFF10\r\n   Name     - NR 10\r\n   Contents - Sound Mode 1 register, Sweep register (R/W)\r\n\r\n              Bit 6-4 - Sweep Time\r\n              Bit 3   - Sweep Increase/Decrease\r\n                         0: Addition    (frequency increases)\r\n                         1: Subtraction (frequency decreases)\r\n              Bit 2-0 - Number of sweep shift (n: 0-7)\r\n\r\n              Sweep Time: 000: sweep off - no freq change\r\n                          001: 7.8 ms  (1/128Hz)\r\n                          010: 15.6 ms (2/128Hz)\r\n                          011: 23.4 ms (3/128Hz)\r\n                          100: 31.3 ms (4/128Hz)\r\n                          101: 39.1 ms (5/128Hz)\r\n                          110: 46.9 ms (6/128Hz)\r\n                          111: 54.7 ms (7/128Hz)\r\n\r\n              The change of frequency (NR13,NR14) at each shift\r\n              is calculated by the following formula where\r\n              X(0) is initial freq & X(t-1) is last freq:\r\n\r\n               X(t) = X(t-1) +/- X(t-1)/2^n\r\n\r\nFF11\r\n   Name     - NR 11\r\n   Contents - Sound Mode 1 register, Sound length/Wave pattern duty (R/W)\r\n\r\n              Only Bits 7-6 can be read.\r\n\r\n              Bit 7-6 - Wave Pattern Duty\r\n              Bit 5-0 - Sound length data (t1: 0-63)\r\n\r\n              Wave Duty: 00: 12.5% ( _--------_--------_-------- )\r\n                         01: 25%   ( __-------__-------__------- )\r\n                         10: 50%   ( ____-----____-----____----- ) (default)\r\n                         11: 75%   ( ______---______---______--- )\r\n\r\n              Sound Length = (64-t1)*(1/256) seconds\r\nFF12\r\n   Name     - NR 12\r\n   Contents - Sound Mode 1 register, Envelope (R/W)\r\n\r\n              Bit 7-4 - Initial volume of envelope\r\n              Bit 3 -   Envelope UP/DOWN\r\n                         0: Attenuate\r\n                         1: Amplify\r\n              Bit 2-0 - Number of envelope sweep (n: 0-7)\r\n                        (If zero, stop envelope operation.)\r\n\r\n              Initial volume of envelope is from 0 to $F.\r\n              Zero being no sound.\r\n\r\n              Length of 1 step = n*(1/64) seconds\r\n\r\nFF13\r\n   Name     - NR 13\r\n   Contents - Sound Mode 1 register, Frequency lo (W)\r\n\r\n              Lower 8 bits of 11 bit frequency (x).\r\n              Next 3 bit are in NR 14 ($FF14)\r\n\r\nFF14\r\n   Name     - NR 14\r\n   Contents - Sound Mode 1 register, Frequency hi (R/W)\r\n\r\n              Only Bit 6 can be read.\r\n\r\n              Bit 7 - Initial (when set, sound restarts)\r\n              Bit 6 - Counter/consecutive selection\r\n              Bit 2-0 - Frequency's higher 3 bits (x)\r\n\r\n              Frequency = 4194304/(32*(2048-x)) Hz\r\n                        = 131072/(2048-x) Hz\r\n\r\n              Counter/consecutive Selection\r\n               0 = Regardless of the length data in NR11\r\n                   sound can be produced consecutively.\r\n               1 = Sound is generated during the time period\r\n                   set by the length data in NR11. After this\r\n                   period the sound 1 ON flag (bit 0 of NR52)\r\n                   is reset.\r\n\r\nFF16\r\n   Name     - NR 21\r\n   Contents - Sound Mode 2 register, Sound Length; Wave Pattern Duty (R/W)\r\n\r\n              Only bits 7-6 can be read.\r\n\r\n              Bit 7-6 - Wave pattern duty\r\n              Bit 5-0 - Sound length data (t1: 0-63)\r\n\r\n              Wave Duty: 00: 12.5% ( _--------_--------_-------- )\r\n                         01: 25%   ( __-------__-------__------- )\r\n                         10: 50%   ( ____-----____-----____----- ) (default)\r\n                         11: 75%   ( ______---______---______--- )\r\n\r\n              Sound Length = (64-t1)*(1/256) seconds\r\n\r\nFF17\r\n   Name     - NR 22\r\n   Contents - Sound Mode 2 register, envelope (R/W)\r\n\r\n              Bit 7-4 - Initial volume of envelope\r\n              Bit 3 -   Envelope UP/DOWN\r\n                         0: Attenuate\r\n                         1: Amplify\r\n              Bit 2-0 - Number of envelope sweep (n: 0-7)\r\n                        (If zero, stop envelope operation.)\r\n\r\n              Initial volume of envelope is from 0 to $F.\r\n              Zero being no sound.\r\n\r\n              Length of 1 step = n*(1/64) seconds\r\n\r\nFF18\r\n   Name     - NR 23\r\n   Contents - Sound Mode 2 register, frequency lo data (W)\r\n\r\n              Frequency's lower 8 bits of 11 bit data (x).\r\n              Next 3 bits are in NR 14 ($FF19).\r\n\r\nFF19\r\n   Name     - NR 24\r\n   Contents - Sound Mode 2 register, frequency hi data (R/W)\r\n\r\n              Only bit 6 can be read.\r\n\r\n              Bit 7 - Initial (when set, sound restarts)\r\n              Bit 6 - Counter/consecutive selection\r\n              Bit 2-0 - Frequency's higher 3 bits (x)\r\n\r\n              Frequency = 4194304/(32*(2048-x)) Hz\r\n                        = 131072/(2048-x) Hz\r\n\r\n              Counter/consecutive Selection\r\n               0 = Regardless of the length data in NR21\r\n                   sound can be produced consecutively.\r\n               1 = Sound is generated during the time period\r\n                   set by the length data in NR21. After this\r\n                   period the sound 2 ON flag (bit 1 of NR52)\r\n                   is reset.\r\n\r\nFF1A\r\n   Name     - NR 30\r\n   Contents - Sound Mode 3 register, Sound on/off (R/W)\r\n\r\n              Only bit 7 can be read\r\n\r\n              Bit 7 - Sound OFF\r\n                      0: Sound 3 output stop\r\n                      1: Sound 3 output OK\r\n\r\nFF1B\r\n   Name     - NR 31\r\n   Contents - Sound Mode 3 register, sound length (R/W)\r\n\r\n              Bit 7-0 - Sound length (t1: 0 - 255)\r\n\r\n              Sound Length = (256-t1)*(1/2) seconds\r\n\r\nFF1C\r\n   Name     - NR 32\r\n   Contents - Sound Mode 3 register, Select output level (R/W)\r\n\r\n              Only bits 6-5 can be read\r\n\r\n              Bit 6-5 - Select output level\r\n                        00: Mute\r\n                        01: Produce Wave Pattern RAM Data as it is\r\n                            (4 bit length)\r\n                        10: Produce Wave Pattern RAM data shifted once\r\n                            to the RIGHT (1/2)  (4 bit length)\r\n                        11: Produce Wave Pattern RAM data shifted twice\r\n                            to the RIGHT (1/4)  (4 bit length)\r\n\r\n       * - Wave Pattern RAM is located from $FF30-$FF3f.\r\n\r\nFF1D\r\n   Name     - NR 33\r\n   Contents - Sound Mode 3 register, frequency's lower data (W)\r\n\r\n              Lower 8 bits of an 11 bit frequency (x).\r\n\r\nFF1E\r\n   Name     - NR 34\r\n   Contents - Sound Mode 3 register, frequency's higher data (R/W)\r\n\r\n              Only bit 6 can be read.\r\n\r\n              Bit 7 - Initial (when set, sound restarts)\r\n              Bit 6 - Counter/consecutive flag\r\n              Bit 2-0 - Frequency's higher 3 bits (x).\r\n\r\n              Frequency = 4194304/(64*(2048-x)) Hz\r\n                        = 65536/(2048-x) Hz\r\n\r\n              Counter/consecutive Selection\r\n               0 = Regardless of the length data in NR31\r\n                   sound can be produced consecutively.\r\n               1 = Sound is generated during the time period\r\n                   set by the length data in NR31. After this\r\n                   period the sound 3 ON flag (bit 2 of NR52)\r\n                   is reset.\r\n\r\nFF20\r\n   Name     - NR 41\r\n   Contents - Sound Mode 4 register, sound length (R/W)\r\n\r\n              Bit 5-0 - Sound length data (t1: 0-63)\r\n\r\n              Sound Length = (64-t1)*(1/256) seconds\r\n\r\nFF21\r\n   Name     - NR 42\r\n   Contents - Sound Mode 4 register, envelope (R/W)\r\n\r\n              Bit 7-4 - Initial volume of envelope\r\n              Bit 3 -   Envelope UP/DOWN\r\n                         0: Attenuate\r\n                         1: Amplify\r\n              Bit 2-0 - Number of envelope sweep (n: 0-7)\r\n                        (If zero, stop envelope operation.)\r\n\r\n              Initial volume of envelope is from 0 to $F.\r\n              Zero being no sound.\r\n\r\n              Length of 1 step = n*(1/64) seconds\r\n\r\nFF22\r\n   Name     - NR 43\r\n   Contents - Sound Mode 4 register, polynomial counter (R/W)\r\n\r\n              Bit 7-4 - Selection of the shift clock frequency of the\r\n                        polynomial counter\r\n              Bit 3   - Selection of the polynomial counter's step\r\n              Bit 2-0 - Selection of the dividing ratio of frequencies\r\n\r\n              Selection of the dividing ratio of frequencies:\r\n              000: f * 1/2^3 * 2\r\n              001: f * 1/2^3 * 1\r\n              010: f * 1/2^3 * 1/2\r\n              011: f * 1/2^3 * 1/3\r\n              100: f * 1/2^3 * 1/4\r\n              101: f * 1/2^3 * 1/5\r\n              110: f * 1/2^3 * 1/6\r\n              111: f * 1/2^3 * 1/7           f = 4.194304 Mhz\r\n\r\n              Selection of the polynomial counter step:\r\n              0: 15 steps\r\n              1: 7 steps\r\n\r\n              Selection of the shift clock frequency of the polynomial\r\n              counter:\r\n\r\n              0000: dividing ratio of frequencies * 1/2\r\n              0001: dividing ratio of frequencies * 1/2^2\r\n              0010: dividing ratio of frequencies * 1/2^3\r\n              0011: dividing ratio of frequencies * 1/2^4\r\n                    :                          :\r\n                    :                          :\r\n                    :                          :\r\n              0101: dividing ratio of frequencies * 1/2^14\r\n              1110: prohibited code\r\n              1111: prohibited code\r\n\r\nFF23\r\n   Name     - NR 44\r\n   Contents - Sound Mode 4 register, counter/consecutive; inital (R/W)\r\n\r\n              Only bit 6 can be read.\r\n\r\n              Bit 7 - Initial (when set, sound restarts)\r\n              Bit 6 - Counter/consecutive selection\r\n\r\n              Counter/consecutive Selection\r\n               0 = Regardless of the length data in NR41\r\n                   sound can be produced consecutively.\r\n               1 = Sound is generated during the time period\r\n                   set by the length data in NR41. After this\r\n                   period the sound 4 ON flag (bit 3 of NR52)\r\n                   is reset.\r\n\r\nFF24\r\n   Name     - NR 50\r\n   Contents - Channel control / ON-OFF / Volume (R/W)\r\n\r\n              Bit 7 - Vin->SO2 ON/OFF\r\n              Bit 6-4 - SO2 output level (volume) (# 0-7)\r\n              Bit 3 - Vin->SO1 ON/OFF\r\n              Bit 2-0 - SO1 output level (volume) (# 0-7)\r\n\r\n              Vin->SO1 (Vin->SO2)\r\n\r\n              By synthesizing the sound from sound 1\r\n              through 4, the voice input from Vin\r\n              terminal is put out.\r\n              0: no output\r\n              1: output OK\r\n\r\nFF25\r\n    Name     - NR 51\r\n    Contents - Selection of Sound output terminal (R/W)\r\n\r\n               Bit 7 - Output sound 4 to SO2 terminal\r\n               Bit 6 - Output sound 3 to SO2 terminal\r\n               Bit 5 - Output sound 2 to SO2 terminal\r\n               Bit 4 - Output sound 1 to SO2 terminal\r\n               Bit 3 - Output sound 4 to SO1 terminal\r\n               Bit 2 - Output sound 3 to SO1 terminal\r\n               Bit 1 - Output sound 2 to SO1 terminal\r\n               Bit 0 - Output sound 1 to SO1 terminal\r\n\r\nFF26\r\n    Name     - NR 52  (Value at reset: $F1-GB, $F0-SGB)\r\n    Contents - Sound on/off (R/W)\r\n\r\n               Bit 7 - All sound on/off\r\n                       0: stop all sound circuits\r\n                       1: operate all sound circuits\r\n               Bit 3 - Sound 4 ON flag\r\n               Bit 2 - Sound 3 ON flag\r\n               Bit 1 - Sound 2 ON flag\r\n               Bit 0 - Sound 1 ON flag\r\n\r\n                Bits 0 - 3 of this register are meant to\r\n               be status bits to be read. Writing to these\r\n               bits does NOT enable/disable sound.\r\n\r\n                If your GB programs don't use sound then\r\n               write $00 to this register to save 16% or\r\n               more on GB power consumption.\r\nFF30 - FF3F\r\n   Name     - Wave Pattern RAM\r\n   Contents - Waveform storage for arbitrary sound data\r\n\r\n              This storage area holds 32 4-bit samples\r\n              that are played back upper 4 bits first.\r\n\r\nFF40\r\n   Name     - LCDC  (value $91 at reset)\r\n   Contents - LCD Control (R/W)\r\n\r\n              Bit 7 - LCD Control Operation *\r\n                      0: Stop completely (no picture on screen)\r\n                      1: operation\r\n\r\n              Bit 6 - Window Tile Map Display Select\r\n                      0: $9800-$9BFF\r\n                      1: $9C00-$9FFF\r\n\r\n              Bit 5 - Window Display\r\n                      0: off\r\n                      1: on\r\n\r\n              Bit 4 - BG & Window Tile Data Select\r\n                      0: $8800-$97FF\r\n                      1: $8000-$8FFF <- Same area as OBJ\r\n\r\n              Bit 3 - BG Tile Map Display Select\r\n                      0: $9800-$9BFF\r\n                      1: $9C00-$9FFF\r\n\r\n              Bit 2 - OBJ (Sprite) Size\r\n                      0: 8*8\r\n                      1: 8*16 (width*height)\r\n\r\n              Bit 1 - OBJ (Sprite) Display\r\n                      0: off\r\n                      1: on\r\n\r\n              Bit 0 - BG Display\r\n                      0: off\r\n                      1: on\r\n\r\n       * - Stopping LCD operation (bit 7 from 1 to 0)\r\n           must be performed during V-blank to work\r\n           properly. V-blank can be confirmed when the\r\n           value of LY is greater than or equal to 144.\r\n\r\nFF41\r\n   Name     - STAT\r\n   Contents - LCDC Status   (R/W)\r\n\r\n              Bits 6-3 - Interrupt Selection By LCDC Status\r\n\r\n              Bit 6 - LYC=LY Coincidence (Selectable)\r\n              Bit 5 - Mode 10\r\n              Bit 4 - Mode 01\r\n              Bit 3 - Mode 00\r\n                      0: Non Selection\r\n                      1: Selection\r\n\r\n              Bit 2 - Coincidence Flag\r\n                      0: LYC not equal to LCDC LY\r\n                      1: LYC = LCDC LY\r\n\r\n              Bit 1-0 - Mode Flag\r\n                        00: During H-Blank\r\n                        01: During V-Blank\r\n                        10: During Searching OAM-RAM\r\n                        11: During Transfering Data to LCD Driver\r\n\r\n     STAT shows the current status of the LCD controller.\r\n     Mode 00: When the flag is 00 it is the H-Blank period\r\n              and the CPU can access the display RAM\r\n              ($8000-$9FFF).\r\n\r\n     Mode 01: When the flag is 01 it is the V-Blank period\r\n              and the CPU can access the display RAM\r\n              ($8000-$9FFF).\r\n\r\n     Mode 10: When the flag is 10 then the OAM is being\r\n              used ($FE00-$FE9F). The CPU cannot access\r\n              the OAM during this period\r\n\r\n     Mode 11: When the flag is 11 both the OAM and display\r\n              RAM are being used. The CPU cannot access\r\n              either during this period.\r\n\r\n\r\n     The following are typical when the display is enabled:\r\n\r\nMode 0  000___000___000___000___000___000___000________________\r\nMode 1  _______________________________________11111111111111__\r\nMode 2  ___2_____2_____2_____2_____2_____2___________________2_\r\nMode 3  ____33____33____33____33____33____33__________________3\r\n\r\n\r\n       The Mode Flag goes through the values 0, 2,\r\n      and 3 at a cycle of about 109uS. 0 is present\r\n      about 48.6uS, 2 about 19uS, and 3 about 41uS. This\r\n      is interrupted every 16.6ms by the VBlank (1).\r\n      The mode flag stays set at 1 for about 1.08 ms.\r\n      (Mode 0 is present between 201-207 clks, 2 about\r\n       77-83 clks, and 3 about 169-175 clks. A complete\r\n       cycle through these states takes 456 clks.\r\n       VBlank lasts 4560 clks. A complete screen refresh\r\n       occurs every 70224 clks.)\r\n\r\nFF42\r\n   Name     - SCY\r\n   Contents - Scroll Y   (R/W)\r\n\r\n              8 Bit value $00-$FF to scroll BG Y screen\r\n              position.\r\n\r\nFF43\r\n   Name     - SCX\r\n   Contents - Scroll X   (R/W)\r\n\r\n              8 Bit value $00-$FF to scroll BG X screen\r\n              position.\r\n\r\nFF44\r\n   Name     - LY\r\n   Contents - LCDC Y-Coordinate (R)\r\n\r\n            The LY indicates the vertical line to which\r\n            the present data is transferred to the LCD\r\n            Driver. The LY can take on any value between\r\n            0 through 153. The values between 144 and 153\r\n            indicate the V-Blank period. Writing will\r\n            reset the counter.\r\n\r\nFF45\r\n   Name     - LYC\r\n   Contents - LY Compare  (R/W)\r\n\r\n            The LYC compares itself with the LY. If the\r\n            values are the same it causes the STAT to set\r\n            the coincident flag.\r\n\r\nFF46\r\n   Name     - DMA\r\n   Contents - DMA Transfer and Start Address (W)\r\n\r\n   The DMA Transfer (40*28 bit) from internal ROM or RAM\r\n   ($0000-$F19F) to the OAM (address $FE00-$FE9F) can be\r\n   performed. It takes 160 microseconds for the transfer.\r\n\r\n   40*28 bit = #140  or #$8C.  As you can see, it only\r\n   transfers $8C bytes of data. OAM data is $A0 bytes\r\n   long, from $0-$9F.\r\n\r\n   But if you examine the OAM data you see that 4 bits are\r\n   not in use.\r\n\r\n   40*32 bit = #$A0, but since 4 bits for each OAM is not\r\n   used it's 40*28 bit.\r\n\r\n   It transfers all the OAM data to OAM RAM.\r\n\r\n   The DMA transfer start address can be designated every\r\n   $100 from address $0000-$F100. That means $0000, $0100,\r\n   $0200, $0300....\r\n\r\n    As can be seen by looking at register $FF41 Sprite RAM\r\n   ($FE00 - $FE9F) is not always available. A simple routine\r\n   that many games use to write data to Sprite memory is shown\r\n   below. Since it copies data to the sprite RAM at the appro-\r\n   priate times it removes that responsibility from the main\r\n   program.\r\n    All of the memory space, except high ram ($FF80-$FFFE),\r\n   is not accessible during DMA. Because of this, the routine\r\n   below must be copied & executed in high ram. It is usually\r\n   called from a V-blank Interrupt.\r\n\r\n   Example program:\r\n\r\n      org $40\r\n      jp VBlank\r\n\r\n      org $ff80\r\nVBlank:\r\n      push af        <- Save A reg & flags\r\n      ld a,BASE_ADRS <- transfer data from BASE_ADRS\r\n      ld ($ff46),a   <- put A into DMA registers\r\n      ld a,28h       <- loop length\r\nWait:                <- We need to wait 160 microseconds.\r\n      dec a          <-  4 cycles - decrease A by 1\r\n      jr nz,Wait     <- 12 cycles - branch if Not Zero to Wait\r\n      pop af         <- Restore A reg & flags\r\n      reti           <- Return from interrupt\r\n\r\n\r\nFF47\r\n   Name     - BGP\r\n   Contents - BG & Window Palette Data  (R/W)\r\n\r\n              Bit 7-6 - Data for Dot Data 11 (Normally darkest color)\r\n              Bit 5-4 - Data for Dot Data 10\r\n              Bit 3-2 - Data for Dot Data 01\r\n              Bit 1-0 - Data for Dot Data 00 (Normally lightest color)\r\n\r\n              This selects the shade of grays to use for\r\n              the background (BG) & window pixels. Since\r\n              each pixel uses 2 bits, the corresponding\r\n              shade will be selected from here.\r\n\r\nFF48\r\n   Name     - OBP0\r\n   Contents - Object Palette 0 Data (R/W)\r\n\r\n              This selects the colors for sprite palette 0.\r\n              It works exactly as BGP ($FF47) except each\r\n              each value of 0 is transparent.\r\n\r\nFF49\r\n   Name     - OBP1\r\n   Contents - Object Palette 1 Data (R/W)\r\n\r\n              This Selects the colors for sprite palette 1.\r\n              It works exactly as OBP0 ($FF48).\r\n              See BGP for details.\r\n\r\nFF4A\r\n   Name     - WY\r\n   Contents - Window Y Position  (R/W)\r\n\r\n              0 <= WY <= 143\r\n\r\n              WY must be greater than or equal to 0 and\r\n              must be less than or equal to 143 for\r\n              window to be visible.\r\n\r\nFF4B\r\n   Name     - WX\r\n   Contents - Window X Position  (R/W)\r\n\r\n              0 <= WX <= 166\r\n\r\n              WX must be greater than or equal to 0 and\r\n              must be less than or equal to 166 for\r\n              window to be visible.\r\n\r\n              WX is offset from absolute screen coordinates\r\n              by 7. Setting the window to WX=7, WY=0 will\r\n              put the upper left corner of the window at\r\n              absolute screen coordinates 0,0.\r\n\r\n\r\n              Lets say WY = 70 and WX = 87.\r\n              The window would be positioned as so:\r\n\r\n               0                  80               159\r\n               ______________________________________\r\n            0 |                                      |\r\n              |                   |                  |\r\n              |                                      |\r\n              |         Background Display           |\r\n              |               Here                   |\r\n              |                                      |\r\n              |                                      |\r\n           70 |         -         +------------------|\r\n              |                   | 80,70            |\r\n              |                   |                  |\r\n              |                   |  Window Display  |\r\n              |                   |       Here       |\r\n              |                   |                  |\r\n              |                   |                  |\r\n          143 |___________________|__________________|\r\n\r\n\r\n          OBJ Characters (Sprites) can still enter the\r\n          window. None of the window colors are\r\n          transparent so any background tiles under the\r\n          window are hidden.\r\n\r\nFFFF\r\n   Name     - IE\r\n   Contents - Interrupt Enable (R/W)\r\n\r\n              Bit 4: Transition from High to Low of Pin\r\n                     number P10-P13.\r\n              Bit 3: Serial I/O transfer complete\r\n              Bit 2: Timer Overflow\r\n              Bit 1: LCDC (see STAT)\r\n              Bit 0: V-Blank\r\n\r\n              0: disable\r\n              1: enable\r\n```"}}
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