{"push_id":1634145200,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"19eb9b6906ca66fe47dd71dc2b4b08ae00bc7229","before":"055b8ba1f019c8c2372f7abe36f2fd2de7c1fe15","commits":[{"sha":"19eb9b6906ca66fe47dd71dc2b4b08ae00bc7229","author":{"name":"Wesley W. Terpstra","email":"335c2d428a69ab96434ed404eadfac51b77392e1@sifive.com"},"message":"l1tol2: put a flow Q on the exits (#606)\n\nThis Xbar connects the largest components in the design; the cores\r\nand the L2 banks. We already have a full buffer on the core side.\r\nHowever, the valid path going to the L2 comes back as a ready path.\r\nPutting a flow Q also on the outputs of the l1tol2 cuts this path\r\nin half at no cost to IPC.","distinct":true,"url":"https://api.github.com/repos/ucb-bar/rocket-chip/commits/19eb9b6906ca66fe47dd71dc2b4b08ae00bc7229"}]}
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