{"push_id":1578997838,"size":26,"distinct_size":26,"ref":"refs/heads/master","head":"9e314890292c0dd357eadef6a043704fa0b4c157","before":"f8e6859ea9d06ae1565b21278c4e10fbce5f1eab","commits":[{"sha":"c0fcaf554ed9b65477576439e8de63578d731070","author":{"name":"Jonas Bonn","email":"7f140b51f30eb0762518f611c7ec9a2dd0c91007@southpole.se"},"message":"openrisc: use SPARSE_IRQ\n\nThe sparse IRQ framework is preferred nowadays so switch over to it.\n\nSigned-off-by: Jonas Bonn <jonas@southpole.se>\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/c0fcaf554ed9b65477576439e8de63578d731070"},{"sha":"3e06a16339303016b2c57b350a15afeaa7ba7813","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add cache way information to cpuinfo\n\nMotivation for this is to be able to print the way information\nproperly in print_cpuinfo(), instead of hardcoding it to one.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\nSigned-off-by: Jonas Bonn <jonas@southpole.se>\n[shorne@gmail.com fixed conflict with show_cpuinfo change]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/3e06a16339303016b2c57b350a15afeaa7ba7813"},{"sha":"742fb582b4540a7b59427dc67be1fe4a5eac7078","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: tlb miss handler optimizations\n\nBy slightly reorganizing the code, the number of registers\nused in the tlb miss handlers can be reduced by two,\nthus removing the need to save them to memory.\n\nAlso, some dead and commented out code is removed.\n\nNo functional change.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\nSigned-off-by: Jonas Bonn <jonas@southpole.se>\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/742fb582b4540a7b59427dc67be1fe4a5eac7078"},{"sha":"c2dc72437a5504bf8f4343ed83ae745afa388522","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: head: use THREAD_SIZE instead of magic constant\n\nThe stack size was hard coded to 0x2000, use the standard THREAD_SIZE\ndefinition loaded from thread_info.h.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: Added body to the commit message]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/c2dc72437a5504bf8f4343ed83ae745afa388522"},{"sha":"8c9b7db0de3d64c9a6fcd12622636d4aa6a8c30c","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: head: refactor out tlb flush into it's own function\n\nThis brings it inline with the other setup oprations done like the cache\nenables _ic_enable and _dc_enable.  Also, this is going to make it\neasier to initialize additional cpu's when smp is introduced.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: Added commit body]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/8c9b7db0de3d64c9a6fcd12622636d4aa6a8c30c"},{"sha":"63104c06a9eddf53f88f6d16196bb036c62967b2","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add l.lwa/l.swa emulation\n\nThis adds an emulation layer for implementations\nthat lack the l.lwa and l.swa instructions.\nIt handles these instructions both in kernel space and\nuser space.\n\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: Added delay slot pc adjust logic]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/63104c06a9eddf53f88f6d16196bb036c62967b2"},{"sha":"0e9f9fd20ce931cc2cf0519c56ae33fc74d656ad","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add atomic bitops\n\nThis utilize the load-link/store-conditional l.lwa and l.swa\ninstructions to implement the atomic bitops.\nWhen those instructions are not available emulation is provided.\n\nAcked-by: Peter Zijlstra (Intel) <peterz@infradead.org>\nCc: Peter Zijlstra <peterz@infradead.org>\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by\nAlan Cox https://lkml.org/lkml/2014/7/23/666, implement\ntest_and_change_bit]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/0e9f9fd20ce931cc2cf0519c56ae33fc74d656ad"},{"sha":"11595172537788f0007bfc16590aab18f2b9c40f","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add cmpxchg and xchg implementations\n\nOptimized version that make use of the l.lwa and l.swa atomic instruction\npair.\nMost openrisc cores provide these instructions now, if not available\nemulation is provided.\n\nAcked-by: Peter Zijlstra (Intel) <peterz@infradead.org>\nCc: Peter Zijlstra <peterz@infradead.org>\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by\nAlan Cox https://lkml.org/lkml/2014/7/23/666]\n[shorne@gmail.com: fixed unused calculated value compiler warning in\ndefine cmpxchg]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/11595172537788f0007bfc16590aab18f2b9c40f"},{"sha":"bc19598f1dde267e5214e386b97bb647973275db","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add optimized atomic operations\n\nUsing the l.lwa and l.swa atomic instruction pair.\nMost openrisc processor cores provide these instructions now. If the\ninstructions are not available emulation is provided.\n\nAcked-by: Peter Zijlstra (Intel) <peterz@infradead.org>\nCc: Peter Zijlstra <peterz@infradead.org>\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by\nAlan Cox https://lkml.org/lkml/2014/7/23/666]\n[shorne@gmail.com: expand to implement all ops suggested by Peter\nZijlstra https://lkml.org/lkml/2017/2/20/317]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/bc19598f1dde267e5214e386b97bb647973275db"},{"sha":"4ac46db1aaf16a009a8318cdba3acf03de85bcea","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: add futex_atomic_* implementations\n\nSupport for the futex_atomic_* operations by using the\nload-link/store-conditional l.lwa/l.swa instructions.\nMost openrisc cores provide these instructions now if not available,\nemulation is provided.\n\nAcked-by: Peter Zijlstra (Intel) <peterz@infradead.org>\nCc: Peter Zijlstra <peterz@infradead.org>\nSigned-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>\n[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by\nAlan Cox https://lkml.org/lkml/2014/7/23/666]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/4ac46db1aaf16a009a8318cdba3acf03de85bcea"},{"sha":"89c94fdb9718d8ff3243faf8133a2176fd91f207","author":{"name":"Stefan Kristiansson","email":"d59a80c6e4935445aae5b0854ea45ee8c5843640@saunalahti.fi"},"message":"openrisc: remove unnecessary stddef.h include\n\nThis causes the build to fail when building with the or1k-musl-linux-\ntoolchain and it is not needed.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/89c94fdb9718d8ff3243faf8133a2176fd91f207"},{"sha":"79f8a4d022f2d11d4fc90f785f575ac331e2ef71","author":{"name":"Sebastian Macke","email":"b41fc187c6555e69a919eebe4470829dcc170cca@macke.de"},"message":"openrisc: Fix the bitmask for the unit present register\n\nThe bits were swapped, as per spec and processor implementation the\npower management present bit is 9 and PIC bit is 8. This patch brings\nthe definitions into spec.\n\nSigned-off-by: Sebastian Macke <sebastian@macke.de>\n[shorne@gmail.com: Added commit body]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/79f8a4d022f2d11d4fc90f785f575ac331e2ef71"},{"sha":"e29d11c6991d078bf2011f25dc8c19a2f38c4c8e","author":{"name":"Sebastian Macke","email":"b41fc187c6555e69a919eebe4470829dcc170cca@macke.de"},"message":"openrisc: Initial support for the idle state\n\nThis patch adds basic support for the idle state of the cpu.\nThe patch overrides the regular idle function, enables the interupts,\nchecks for the power management unit and enables the cpu doze mode\nif available.\n\nSigned-off-by: Sebastian Macke <sebastian@macke.de>\n[shorne@gmail.com: Fixed checkpatch, blankline after declarations]\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/e29d11c6991d078bf2011f25dc8c19a2f38c4c8e"},{"sha":"d857a1e253498feb231173218df26f5562c70f09","author":{"name":"Olof Kindgren","email":"9d60b9cec2e9ab3e34936fb3fc3df61e0d5bded1@gmail.com"},"message":"openrisc: Add optimized memset\n\nThis adds a hand-optimized assembler version of memset and sets\n__HAVE_ARCH_MEMSET to use this version instead of the generic C\nroutine\n\nSigned-off-by: Olof Kindgren <olof.kindgren@gmail.com>\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/d857a1e253498feb231173218df26f5562c70f09"},{"sha":"f5d45dc9116b17ee830d3425ece1e9485c9bab88","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"openrisc: Add optimized memcpy routine\n\nThe generic memcpy routine provided in kernel does only byte copies.\nUsing word copies we can lower boot time and cycles spend in memcpy\nquite significantly.\n\nBooting on my de0 nano I see boot times go from 7.2 to 5.6 seconds.\nThe avg cycles in memcpy during boot go from 6467 to 1887.\n\nI tested several algorithms (see code in previous patch mails)\n\nThe implementations I tested and avg cycles:\n  - Word Copies + Loop Unrolls + Non Aligned    1882\n  - Word Copies + Loop Unrolls                  1887\n  - Word Copies                                 2441\n  - Byte Copies + Loop Unrolls                  6467\n  - Byte Copies                                 7600\n\nIn the end I ended up going with Word Copies + Loop Unrolls as it\nprovides best tradeoff between simplicity and boot speedups.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/f5d45dc9116b17ee830d3425ece1e9485c9bab88"},{"sha":"f52092831b0713e1e2b934fe08460f1348f31888","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"openrisc: Add .gitignore\n\nThis helps to suppress the vmlinux.lds file.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/f52092831b0713e1e2b934fe08460f1348f31888"},{"sha":"9dfc96d72b879ebda9a0ed830af6aeee0141943d","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"MAINTAINERS: Add the openrisc official repository\n\nThe openrisc official repository and patch work happens currently on\ngithub. Add the repo for reference.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/9dfc96d72b879ebda9a0ed830af6aeee0141943d"},{"sha":"f72deab378db8eadb6d6eb06b6e2b90c9b681c81","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"scripts/checkstack.pl: Add openrisc support\n\nOpenrisc stack pointer is managed by decrementing r1. Add regexes to\nrecognize this.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/f72deab378db8eadb6d6eb06b6e2b90c9b681c81"},{"sha":"2ead7aba44e973b313fde0e39371363459cc1128","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"openrisc: entry: Whitespace and comment cleanups\n\nCleanups to whitespace and add some comments. Reading through the delay\nslot logic I noticed some things:\n - Delay slot instructions were not indented\n - Some comments are not lined up\n - Use tabs and spaces consistent with other code\n\nNo functional change\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/2ead7aba44e973b313fde0e39371363459cc1128"},{"sha":"e6d20c55a4d94eca419f80f996133f523ecedfe0","author":{"name":"Stafford Horne","email":"818f544dc2537daf9cd8710ad59a9c0bee46870c@gmail.com"},"message":"openrisc: entry: Fix delay slot detection\n\nUse execption SR stored in pt_regs for detection, the current SR is not\ncorrect as the handler is running after return from exception.\n\nAlso, The code that checks for a delay slot uses a flag bitmask and then\nwants to check if the result is not zero.  The test it implemented was\nwrong.\n\nCorrect it by changing the test to check result against non zero.\n\nSigned-off-by: Stafford Horne <shorne@gmail.com>","distinct":true,"url":"https://api.github.com/repos/nmenon/linux-2.6-playground/commits/e6d20c55a4d94eca419f80f996133f523ecedfe0"}]}
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