{"action":"opened","number":805,"pull_request":{"url":"https://api.github.com/repos/virtualagc/virtualagc/pulls/805","id":113844224,"html_url":"https://github.com/virtualagc/virtualagc/pull/805","diff_url":"https://github.com/virtualagc/virtualagc/pull/805.diff","patch_url":"https://github.com/virtualagc/virtualagc/pull/805.patch","issue_url":"https://api.github.com/repos/virtualagc/virtualagc/issues/805","number":805,"state":"open","locked":false,"title":"Simulation of the TC Trap bug, and corrected phasings","user":{"login":"thewonderidiot","id":94056,"avatar_url":"https://avatars3.githubusercontent.com/u/94056?v=3","gravatar_id":"","url":"https://api.github.com/users/thewonderidiot","html_url":"https://github.com/thewonderidiot","followers_url":"https://api.github.com/users/thewonderidiot/followers","following_url":"https://api.github.com/users/thewonderidiot/following{/other_user}","gists_url":"https://api.github.com/users/thewonderidiot/gists{/gist_id}","starred_url":"https://api.github.com/users/thewonderidiot/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/thewonderidiot/subscriptions","organizations_url":"https://api.github.com/users/thewonderidiot/orgs","repos_url":"https://api.github.com/users/thewonderidiot/repos","events_url":"https://api.github.com/users/thewonderidiot/events{/privacy}","received_events_url":"https://api.github.com/users/thewonderidiot/received_events","type":"User","site_admin":false},"body":"This pull request contains two separate, though related, fidelity improvements to yaAGC:\r\n\r\n1. The phasings of the standby PRO button circuit and all five timers were incorrect relative to the scaler (though the periods of all and the phasing of the timers relative to each other were correct). After these changes, all things clocked from the scaler are phased correctly as per the schematics. However, without simulation of the possible TC Trap hardware bug described in #629, these corrected phasings render Aurora and Sunburst unable to pass their self-tests.\r\n2. The three primary causes of said TC Trap bug are now simulated. They are:\r\n    * BZF being taken to an instruction other than EXTEND\r\n    * CS, XCH, TS, and DXCH being executed at all\r\n    * RELINT or INHINT executing after a BZF/BZMF\r\n\r\nIt is my hope that the circuit descriptions and timing diagrams contained in ND-1021042 and/or ND-1021043 will prove the hardware sim's timings either correct or incorrect. If we can show with the manuals that the timings of FS10/F10A/F10B and the TC Trap are correct, then I think it's safe to say that the bug must have been present, since I think it is safe to assume that Aurora and Sunburst could in fact pass their tests.\r\n\r\nAnyways, let's leave this open until we get scans of those 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