{"action":"reopened","issue":{"url":"https://api.github.com/repos/espressif/esp-idf/issues/1110","repository_url":"https://api.github.com/repos/espressif/esp-idf","labels_url":"https://api.github.com/repos/espressif/esp-idf/issues/1110/labels{/name}","comments_url":"https://api.github.com/repos/espressif/esp-idf/issues/1110/comments","events_url":"https://api.github.com/repos/espressif/esp-idf/issues/1110/events","html_url":"https://github.com/espressif/esp-idf/issues/1110","id":264869128,"number":1110,"title":"APLL / GPIO16_EMAC_CLK_OUT - wrong frequency - unable to generate 50MHz clk with rev0 chip","user":{"login":"sauttefk","id":776799,"avatar_url":"https://avatars3.githubusercontent.com/u/776799?v=4","gravatar_id":"","url":"https://api.github.com/users/sauttefk","html_url":"https://github.com/sauttefk","followers_url":"https://api.github.com/users/sauttefk/followers","following_url":"https://api.github.com/users/sauttefk/following{/other_user}","gists_url":"https://api.github.com/users/sauttefk/gists{/gist_id}","starred_url":"https://api.github.com/users/sauttefk/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sauttefk/subscriptions","organizations_url":"https://api.github.com/users/sauttefk/orgs","repos_url":"https://api.github.com/users/sauttefk/repos","events_url":"https://api.github.com/users/sauttefk/events{/privacy}","received_events_url":"https://api.github.com/users/sauttefk/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":4,"created_at":"2017-10-12T09:18:29Z","updated_at":"2017-10-13T10:17:01Z","closed_at":null,"author_association":"NONE","body":"I want to use the APLL to generate the required 50MHz for an external Ethernet PHY using the APLL and the EMAC_CLK_OUT on GPIO16.\r\n\r\n### Somehow the output frequency is unexpectedly divided by 5\r\n\r\nAccording to  the [_ECO and Workarounds for Bugs in ESP32_ (issue 3.7)](https://espressif.com/sites/default/files/documentation/eco_and_workarounds_for_bugs_in_esp32_en.pdf) document the formula for the APLL frequency for rev0 chips is:\r\n`f_out = f_xtal × (sdm2 + 4) / (2 × (o_div + 2))` where `f_xtal` is **40MHz**, `sdm2` is **6** (4th parameter), o_div is **2** (5th parameter).\r\nThis evaluates to `f_out = 40MHz × (6 + 4) / (2 × (2 + 2))` =>` f_out = 400MHz / 8` => `f_out = 50MHz`\r\nAccording to the [_ESP32 Technical Reference Manual_ (paragraph 3.2.7)](http://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf) the dividend of the formula (`f_xtal × (sdm2 + 4)`) has a frequency range from 350MHz to 500MHz (Where 400MHz lies well within).\r\n\r\nI'm setting up set the correct parameters with `rtc_clk_apll_enable(1, 0, 0, 6, 2)` but the frequency I get on `GPIO16` is **10MHz** instead of **50MHz**.\r\n\r\nWhen I change `o_div` from **2** to **0**, I get **20MHz** (which prooves that the divisor works as described).\r\nWhen I change `sdm2` from **6** to **8**, I get **12MHz** (which prooves that the dividend works as described in the formula).\r\nWhen I change `sdm2` to **1** and `o_div` to **0** (`rtc_clk_apll_enable(1, 0, 0, 1, 0)`) - this also evaluates to 50MHz - the function call never returns, as the dividend now gets 200MHz which is out of the frequency range of the APLL but rtc_clk_apll_enable waits for a PLL-lock which never happens (which prooves that the dividend is lower than the specified minimum).\r\nWhen I change `sdm2` to **11** and `o_div` to **4**  (`rtc_clk_apll_enable(1, 0, 0, 11, 4)`) - this also evaluates to 50MHz - but the dividend is now 600MHz and the PLL gets no lock (which prooves that the dividend is higher than the specified maximum).\r\n\r\n**My questions:**\r\n* Is there any by 5 divider which has to be disabled?\r\n* Is the APLL somehow using the internal 8MHz clock instead of the external 40MHz crystal?\r\n* Can anybody provide me some code that generates a 50MHz clk on GPIO16?\r\n\r\nThe code that I'm currently using is as follows:\r\n```\r\n#include \"soc/rtc.h\"\r\n#include \"soc/emac_ex_reg.h\"\r\n\r\nESP_LOGD(TAG, \"################ set up EMAC_CLK_OUT #############\");\r\nPIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);\r\nREG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);\r\nREG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);\r\nREG_CLR_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);\r\nREG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_INT_OSC_EN);\r\nESP_LOGD(TAG, \"################ before enabling APLL ############\");\r\nrtc_clk_apll_enable(1, 0, 0, 6, 2); // 50 MHz\r\nESP_LOGD(TAG, \"################ APLL has a stable lock ##########\");\r\n\r\n```\r\n"}}
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