{"push_id":1503452734,"size":25,"distinct_size":25,"ref":"refs/heads/atomic","head":"9e01e709a0f75e374a7d646fd2aa647d941ca65a","before":"2a0c09540d37db4c3907bcafe81b27ec0802c9af","commits":[{"sha":"60c55505db4acc4a7327928f887e19e8cafd2891","author":{"name":"Xin Tong","email":"d79d844533fefd295f78a1882c1cf1fb9bab71c4@gmail.com"},"message":"Empty line. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292081 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/60c55505db4acc4a7327928f887e19e8cafd2891"},{"sha":"5ec1d7135720fa1ac06b6af35a39009891b72a7e","author":{"name":"Sanjay Patel","email":"8a358757f1b64d62facccc1fd839683fb6856b45@rotateright.com"},"message":"[InstCombine] add tests to show missed vector folds; NFC\n\nAlso, add comments and remove bogus comment.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292082 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/5ec1d7135720fa1ac06b6af35a39009891b72a7e"},{"sha":"ef07090bdfc8837482839ec088588ea79fe28a54","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Fix register class in one of the gather/scatter memory operands so that all 32 bit registers can be allowed.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292087 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ef07090bdfc8837482839ec088588ea79fe28a54"},{"sha":"00915333a90509315898ca5faf8fb6cbaf85fd9e","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD\nwith ZMM index. Similar for SCATTER and the prefetch gather and scatter\ninstructions.\n\nFixes PR31618.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292088 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/00915333a90509315898ca5faf8fb6cbaf85fd9e"},{"sha":"ead90cd47c7b17373c2d3d2dfb32bce9ec1492c3","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Add more gather/scatter encoding test cases.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292089 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ead90cd47c7b17373c2d3d2dfb32bce9ec1492c3"},{"sha":"37b9de50287c515310856344718b0236900b10cb","author":{"name":"Xin Tong","email":"d79d844533fefd295f78a1882c1cf1fb9bab71c4@gmail.com"},"message":"Fix typos. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292092 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/37b9de50287c515310856344718b0236900b10cb"},{"sha":"75deb64c6fc4b4e57c27536c5e04d09b25e33543","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Begin giving the disassembler a way to recognize that VSIB is a different encoding than regular addressing modes.\n\nThis part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292093 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/75deb64c6fc4b4e57c27536c5e04d09b25e33543"},{"sha":"d925138fc651952703e2d4b990ca6728e8d2c152","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[AVX-512] Teach the disassembler about all of the EVEX gather and scatter instructions.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292094 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/d925138fc651952703e2d4b990ca6728e8d2c152"},{"sha":"14d16cc51402a9405de9e30572d79558c1bc7a78","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI\n\nWe were frequently checking for a list of types and the different types\nconveyed no real information. So lump them together explicitly.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292095 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/14d16cc51402a9405de9e30572d79558c1bc7a78"},{"sha":"f031545412013f85af9b1898bc3a4d321a706c0f","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[X86] Merge the disassemblers handling of the different TYPE_RELs by getting the size information from the ENCODING field. NFCI\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292096 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/f031545412013f85af9b1898bc3a4d321a706c0f"},{"sha":"07d3c0f01c56c4fe13ffd6a7194ca4aa0f5513a1","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[InstCombine][SSE] Add DemandedElts support for PSHUFB instructions\n\nSimplify a pshufb shuffle mask based on the elements of the mask that are actually demanded.\n\nDifferential Revision: https://reviews.llvm.org/D28745\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292101 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/07d3c0f01c56c4fe13ffd6a7194ca4aa0f5513a1"},{"sha":"e6bbb863e127ccd2eebf6cb3a8df18627e3fcbc9","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[X86][SSE] Tests showing missing BITREVERSE constant folding\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292111 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/e6bbb863e127ccd2eebf6cb3a8df18627e3fcbc9"},{"sha":"b648fac5ca08156cde1e0c411c0a79a8deff3c28","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[SelectionDAG] Add support for BITREVERSE constant folding\n\nWe were relying on constant folding of the legalized instructions to do what constant folding we had previously\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292114 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/b648fac5ca08156cde1e0c411c0a79a8deff3c28"},{"sha":"dcca2bf4373ff0529b55712b14442bc838dc16e1","author":{"name":"Simon Dardis","email":"2cadd7fe860cffe179363c66eef45424daae0f62@imgtec.com"},"message":"[mips] Correct c.cond.fmt instruction definition.\n\nPermit explicit $fcc<X> operand in c.cond.fmt instruction.\n\nAdd c.cond.fmt to the MIPS to microMIPS instruction mapping table.\n\nCheck that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for\nc.cond.fmt, bc1t, bc1f.\n\nReviewers: seanbruno, zoran.jovanovic, vkalintiris\n\nDifferential Revision: https://reviews.llvm.org/D24510\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292117 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/dcca2bf4373ff0529b55712b14442bc838dc16e1"},{"sha":"2abcd78f2bab75af536136d399a1c596e8f55f59","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[X86][SSE] Test showing missing BITREVERSE knownbits support\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292118 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/2abcd78f2bab75af536136d399a1c596e8f55f59"},{"sha":"3157d2b8a6029fbce7b4257b355e3f555f00930d","author":{"name":"NAKAMURA Takumi","email":"77ecc40bd88f115768eded8d235e9f8d16694cae@gmail.com"},"message":"DWARFDebugInfoTest.cpp: Don't use ArrayRef with initializer. It was allocated locally.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292127 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/3157d2b8a6029fbce7b4257b355e3f555f00930d"},{"sha":"541103a1c606980e91451067f98b00c57c2fbf53","author":{"name":"Tony Jiang","email":"22eb0690b33fb39196df8c8f35fc148e874e6289@ca.ibm.com"},"message":"[PowerPC] Expand ISEL instruction into if-then-else sequence.\n\nGenerally, the ISEL is expanded into if-then-else sequence, in some\ncases (like when the destination register is the same with the true\nor false value register), it may just be expanded into just the if\nor else sequence.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292128 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/541103a1c606980e91451067f98b00c57c2fbf53"},{"sha":"1f7c0c9364eb80b1d3779360f50b5b45212056e5","author":{"name":"Simon Pilgrim","email":"5d82cab8c849387bc8a42783c2e56535c94fed74@redking.me.uk"},"message":"[SelectionDAG] Add knownbits support for BITREVERSE \n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292130 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/1f7c0c9364eb80b1d3779360f50b5b45212056e5"},{"sha":"748e859f36d26fa084a92b38c558be5367a8be47","author":{"name":"Tony Jiang","email":"22eb0690b33fb39196df8c8f35fc148e874e6289@ca.ibm.com"},"message":"Revert \"[PowerPC] Expand ISEL instruction into if-then-else sequence.\"\n\nThis reverts commit 1d0e0374438ca6e153844c683826ba9b82486bb1.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292131 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/748e859f36d26fa084a92b38c558be5367a8be47"},{"sha":"ca24065b988c54406601a50d0e88c7289baf0fce","author":{"name":"Daniel Sanders","email":"11d7e2af1a379271955e5fef131dc5a28fc141a8@apple.com"},"message":"[globalisel] Tablegen-erate current Register Bank Information\n\nSummary:\nAdds a RegisterBank tablegen class that can be used to declare the register\nbanks and an associated tablegen pass to generate the necessary code.\n\nReviewers: t.p.northover, ab, rovka, qcolombet\n\nSubscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka\n\nDifferential Revision: https://reviews.llvm.org/D27338\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292132 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/jvesely/llvm/commits/ca24065b988c54406601a50d0e88c7289baf0fce"}]}
{"actor":{"display_login":"jvesely"}}