{"action":"created","comment":{"url":"https://api.github.com/repos/japaric/cortex-m/pulls/comments/121365452","pull_request_review_id":43406697,"id":121365452,"diff_hunk":"@@ -646,3 +931,122 @@ pub struct Tpiu {\n     /// TPIU Type\n     pub _type: RO<u32>,\n }\n+\n+/// Cache and branch predictor maintenance operations register block\n+#[repr(C)]\n+#[cfg(armv7m)]\n+pub struct Cbp {\n+    /// I-cache invalidate all to PoU\n+    pub iciallu: WO<u32>,\n+    reserved0: RW<u32>,","path":"src/peripheral/mod.rs","position":332,"original_position":332,"commit_id":"97911d9650308ff0a93893898620360327de4a13","original_commit_id":"97911d9650308ff0a93893898620360327de4a13","user":{"login":"adamgreig","id":47219,"avatar_url":"https://avatars1.githubusercontent.com/u/47219?v=3","gravatar_id":"","url":"https://api.github.com/users/adamgreig","html_url":"https://github.com/adamgreig","followers_url":"https://api.github.com/users/adamgreig/followers","following_url":"https://api.github.com/users/adamgreig/following{/other_user}","gists_url":"https://api.github.com/users/adamgreig/gists{/gist_id}","starred_url":"https://api.github.com/users/adamgreig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/adamgreig/subscriptions","organizations_url":"https://api.github.com/users/adamgreig/orgs","repos_url":"https://api.github.com/users/adamgreig/repos","events_url":"https://api.github.com/users/adamgreig/events{/privacy}","received_events_url":"https://api.github.com/users/adamgreig/received_events","type":"User","site_admin":false},"body":":+1:","created_at":"2017-06-12T11:09:59Z","updated_at":"2017-06-12T11:09:59Z","html_url":"https://github.com/japaric/cortex-m/pull/40#discussion_r121365452","pull_request_url":"https://api.github.com/repos/japaric/cortex-m/pulls/40","_links":{"self":{"href":"https://api.github.com/repos/japaric/cortex-m/pulls/comments/121365452"},"html":{"href":"https://github.com/japaric/cortex-m/pull/40#discussion_r121365452"},"pull_request":{"href":"https://api.github.com/repos/japaric/cortex-m/pulls/40"}}},"pull_request":{"url":"https://api.github.com/repos/japaric/cortex-m/pulls/40","id":124788752,"html_url":"https://github.com/japaric/cortex-m/pull/40","diff_url":"https://github.com/japaric/cortex-m/pull/40.diff","patch_url":"https://github.com/japaric/cortex-m/pull/40.patch","issue_url":"https://api.github.com/repos/japaric/cortex-m/issues/40","number":40,"state":"open","locked":false,"title":"Add cache maintenance functions for ARMv7-M","user":{"login":"adamgreig","id":47219,"avatar_url":"https://avatars1.githubusercontent.com/u/47219?v=3","gravatar_id":"","url":"https://api.github.com/users/adamgreig","html_url":"https://github.com/adamgreig","followers_url":"https://api.github.com/users/adamgreig/followers","following_url":"https://api.github.com/users/adamgreig/following{/other_user}","gists_url":"https://api.github.com/users/adamgreig/gists{/gist_id}","starred_url":"https://api.github.com/users/adamgreig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/adamgreig/subscriptions","organizations_url":"https://api.github.com/users/adamgreig/orgs","repos_url":"https://api.github.com/users/adamgreig/repos","events_url":"https://api.github.com/users/adamgreig/events{/privacy}","received_events_url":"https://api.github.com/users/adamgreig/received_events","type":"User","site_admin":false},"body":"This PR adds the cache control primitives, and the higher-level cache maintenance operations that are also present in CMSIS. Cortex-M7 devices generally have a DCache and ICache which can sometimes be useful (mostly if you have external RAM) but you need to specifically clean and invalidate cache entries to ensure coherency between the CPU and DMA or other bus masters.\r\n\r\nSpecifically, this PR:\r\n\r\n* Extends the config flags to include armv7m and armv7em (with -M also being set for -EM parts)\r\n* Puts the existing CLIDR, CTR, CCSIDR, and CSSELR CPUID registers behind cfg(armv7m) as they are only implemented since ARMv7-M.\r\n    * CSSELR is changed to RW - though the table B4-1 says it's RO, the specific information in B4.8.3 says it is RW, and it's used by writing to it.\r\n* Adds methods on CPUID to access those cache related registers and retrieve cache number of sets/ways\r\n* Adds the CBP memory-mapped operations block from Table B2-1, which contains operations to clean and invalidate the instruction and data caches and branch predictor on ARMv7-M parts that include them.\r\n* Adds methods for each of the memory locations in the CBP block to actually perform those operations, with appropriate arguments.\r\n     * Though note the set/way functions are specific to Cortex-M7 and might not apply to a future ARMv7-M implementation with a different cache setup (see the comment in `dcisw()`)\r\n* Adds new methods to SCB that mirror the equivalent SCB_* cache functions in CMSIS (see [core_cm7.h](https://github.com/ARM-software/CMSIS/blob/master/CMSIS/Include/core_cm7.h)).\r\n\r\nAll table/section references refer to the ARMv7-M architecture reference manual.\r\n\r\nTesting that these worked as expected was as fun as you'd imagine but I'm confident they do what's expected and match the CMSIS implementation.\r\n\r\n```\r\nRunning cache test...\r\nOperation               Cache  RAM\r\n----------------------------------\r\nInitial....................A    A\r\nIncrement..................B    B\r\nEnable DCache..............B    B\r\nIncrement..................C    B\r\nClean DCache...............C    C\r\nIncrement..................D    C\r\nInvalidate DCache..........C    C\r\nIncrement..................D    C\r\nCleanInvalidate DCache.....D    D\r\nIncrement..................E    D\r\nClean DCache wrong addr....E    D\r\nClean DCache right addr....E    E\r\nIncrement..................F    E\r\nInval DCache wrong addr....F    E\r\nInval DCache right addr....E    E\r\nIncrement..................F    E\r\nCI DCache wrong addr.......F    E\r\nCI DCache right addr.......F    F\r\nIncrement..................G    F\r\nDisable DCache.............G    G\r\n```\r\n\r\nA few open questions...\r\n\r\n* I'm not super happy at how you have to pass &cpuid into some of the SCB cache methods, but I can't see any nice way around this. The functions are in SCB to match the `SCB_CleanDCache()` macros from CMSIS and because the key cache enable bits are in SCB, but you could imagine moving these to methods on CBP instead.\r\n* The SCB methods currently accesses the CBP block with `get()` but as this whole block is WO, stateless, and just consists of memory-mapped operations, I assume this isn't a problem.\r\n* Calling `invalidate_dcache` while the dcache is enabled is generally a poor idea: your stack including callstack could be reset to some older state among other problems. If you build this with optimisations, `invalidate_dcache` gets inlined and uses registers enough that it will complete and do what you expect, but if the cache contains anything that should have been cleaned you will get some unexpected results. If you build without optimisations, it will just get stuck in the invalidate loop as the loop counter update gets wiped out. I wrote an inlineable asm version which solves this specific problem, but still means your stack will probably not be correct, and it's a bunch messier, so I think this simple non-asm version is the one to use. Since disabling the DCache also does a clean and invalidate afterwards, it's not clear when you'd actually want to call `invalidate_dcache` (outside of `enable_dcache` which calls it before enabling the cache). I included it because it's in CMSIS.","created_at":"2017-06-09T04:20:03Z","updated_at":"2017-06-12T11:09:59Z","closed_at":null,"merged_at":null,"merge_commit_sha":"92a8194582c73d1b633b8f9fce26cfaf90ea3a9a","assignee":null,"assignees":[],"requested_reviewers":[],"milestone":null,"commits_url":"https://api.github.com/repos/japaric/cortex-m/pulls/40/commits","review_comments_url":"https://api.github.com/repos/japaric/cortex-m/pulls/40/comments","review_comment_url":"https://api.github.com/repos/japaric/cortex-m/pulls/comments{/number}","comments_url":"https://api.github.com/repos/japaric/cortex-m/issues/40/comments","statuses_url":"https://api.github.com/repos/japaric/cortex-m/statuses/97911d9650308ff0a93893898620360327de4a13","head":{"label":"adamgreig:cache_control","ref":"cache_control","sha":"97911d9650308ff0a93893898620360327de4a13","user":{"login":"adamgreig","id":47219,"avatar_url":"https://avatars1.githubusercontent.com/u/47219?v=3","gravatar_id":"","url":"https://api.github.com/users/adamgreig","html_url":"https://github.com/adamgreig","followers_url":"https://api.github.com/users/adamgreig/followers","following_url":"https://api.github.com/users/adamgreig/following{/other_user}","gists_url":"https://api.github.com/users/adamgreig/gists{/gist_id}","starred_url":"https://api.github.com/users/adamgreig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/adamgreig/subscriptions","organizations_url":"https://api.github.com/users/adamgreig/orgs","repos_url":"https://api.github.com/users/adamgreig/repos","events_url":"https://api.github.com/users/adamgreig/events{/privacy}","received_events_url":"https://api.github.com/users/adamgreig/received_events","type":"User","site_admin":false},"repo":{"id":93355430,"name":"cortex-m","full_name":"adamgreig/cortex-m","owner":{"login":"adamgreig","id":47219,"avatar_url":"https://avatars1.githubusercontent.com/u/47219?v=3","gravatar_id":"","url":"https://api.github.com/users/adamgreig","html_url":"https://github.com/adamgreig","followers_url":"https://api.github.com/users/adamgreig/followers","following_url":"https://api.github.com/users/adamgreig/following{/other_user}","gists_url":"https://api.github.com/users/adamgreig/gists{/gist_id}","starred_url":"https://api.github.com/users/adamgreig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/adamgreig/subscriptions","organizations_url":"https://api.github.com/users/adamgreig/orgs","repos_url":"https://api.github.com/users/adamgreig/repos","events_url":"https://api.github.com/users/adamgreig/events{/privacy}","received_events_url":"https://api.github.com/users/adamgreig/received_events","type":"User","site_admin":false},"private":false,"html_url":"https://github.com/adamgreig/cortex-m","description":"Low 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