{"push_id":1678783110,"size":56,"distinct_size":56,"ref":"refs/heads/amd-common","head":"f74e35b1293f460bbfc325f3651b7ee7f128179e","before":"3431f686a841e85d206e13dedf237fe2b0aca2a6","commits":[{"sha":"806fd9daca9efb556cf2fd73196e6112cb84e478","author":{"name":"kanarayan","email":"59a3c0ddfed9449ed7cac14964b301e55327cc94@amd.com"},"message":"Fix a problem with the memory legalizer when it tries to look up operations beyond the end of the block.\n\nChange-Id: I11a13db56dde0bef6c7e7ab6b098bc479d825681","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/806fd9daca9efb556cf2fd73196e6112cb84e478"},{"sha":"a35de8936321a8f691938f0631b51b9398b0a8be","author":{"name":"kanarayan","email":"59a3c0ddfed9449ed7cac14964b301e55327cc94@amd.com"},"message":"[AMDGPU] Add barrier surrounded by fences tests\n\nChange-Id: I8f6281013aa8ca372f7571a1f80b88f3df50b720","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/a35de8936321a8f691938f0631b51b9398b0a8be"},{"sha":"4f5f4e9e2a6dd3de9e7fb36047cdd3ab72ace5af","author":{"name":"Serguei Katkov","email":"ed56cddb609a5050031d88b18efd5af602e1bf90@azul.com"},"message":"[BPI] Refactor post domination calculation and simple fix for ColdCall\n\nCollection of PostDominatedByUnreachable and PostDominatedByColdCall have been\nsplit out of heuristics itself. Update of the data happens now for each basic\nblock (before update for PostDominatedByColdCall might be skipped if\nunreachable or matadata heuristic handled this basic block).\n\nThis separation allows re-ordering of heuristics without loosing\nthe post-domination information.\n\nReviewers: sanjoy, junbuml, vsk, chandlerc, reames\n\nReviewed By: chandlerc\n\nSubscribers: llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D31701\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300029 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/4f5f4e9e2a6dd3de9e7fb36047cdd3ab72ace5af"},{"sha":"96d92eadca24761a1379993b197e7476f105bfc9","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[InstCombine][IR] Add a commutable BinOp matcher. Use it to reduce some code. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300030 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/96d92eadca24761a1379993b197e7476f105bfc9"},{"sha":"00b79068c49a8dcc50bac690d0a30f04920faa25","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[IR] Fix copy and paste mistake in comment. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300031 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/00b79068c49a8dcc50bac690d0a30f04920faa25"},{"sha":"ddfada260ad50e3a5ff18f61bed2fd9efadda8d1","author":{"name":"Chandler Carruth","email":"f202c0deeaccee703d9195ab786f78f6938b11a3@gmail.com"},"message":"[IR] Redesign the case iterator in SwitchInst to actually be an iterator\nand to expose a handle to represent the actual case rather than having\nthe iterator return a reference to itself.\n\nAll of this allows the iterator to be used with common STL facilities,\nstandard algorithms, etc.\n\nDoing this exposed some missing facilities in the iterator facade that\nI've fixed and required some work to the actual iterator to fully\nsupport the necessary API.\n\nDifferential Revision: https://reviews.llvm.org/D31548\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300032 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/ddfada260ad50e3a5ff18f61bed2fd9efadda8d1"},{"sha":"3512d22fea43d45b3851c7aad057a2853947345e","author":{"name":"Piotr Padlewski","email":"fb20fa40ab7fd28be20690983960497132f54779@gmail.com"},"message":"Invariant.group and mustalias docs fixes\n\nSummary:\nAlias analysis would like to know that\ninvariant.group.barrier returns pointer that mustalias,\nbut this can't imply that we can replace one pointer with another\n\nReviewers: dberlin, sanjoy\n\nSubscribers: llvm-commits, chandlerc, hfinkel, nlewycky, amharc\n\nDifferential Revision: https://reviews.llvm.org/D31758\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300033 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/3512d22fea43d45b3851c7aad057a2853947345e"},{"sha":"a22205806d257629697325c69d8a166539ddc5e3","author":{"name":"Bjorn Pettersson","email":"267ce3f9ab44a268b3cd2800d6aa5fa7f5b6d40d@ericsson.com"},"message":"[LoadCombine] Avoid analysing dead basic blocks\n\nSummary:\nDead basic blocks may be forming a loop, for which SSA form is\nfulfilled, but with a circular def-use chain. LoadCombine could\nenter an infinite loop when analysing such dead code. This patch\nsolves the problem by simply avoiding to analyse all basic blocks\nthat aren't forward reachable, from function entry, in LoadCombine.\n\nFixes https://bugs.llvm.org/show_bug.cgi?id=27065\n\nReviewers: mehdi_amini, chandlerc, grosser, Bigcheese, davide\n\nReviewed By: davide\n\nSubscribers: dberlin, zzheng, bjope, grandinj, Ka-Ka, materi, jholewinski, llvm-commits, mzolotukhin\n\nDifferential Revision: https://reviews.llvm.org/D31032\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300034 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/a22205806d257629697325c69d8a166539ddc5e3"},{"sha":"81de2d08abea19741a78a14e0288df9975d36998","author":{"name":"Daniel Sanders","email":"11d7e2af1a379271955e5fef131dc5a28fc141a8@apple.com"},"message":"[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand\n\nSummary:\nAs far as instruction selection is concerned, all three appear to be same thing.\n\nSupport for these operands is experimental since AArch64 doesn't make use\nof them and the in-tree targets that do use them (AMDGPU for\nOperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM\nfor OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet.\n\nReviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab\n\nReviewed By: rovka\n\nSubscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D31135\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300037 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/81de2d08abea19741a78a14e0288df9975d36998"},{"sha":"76dc6181d8cbdfa21e8aad36a20c06210a322fd4","author":{"name":"Chandler Carruth","email":"f202c0deeaccee703d9195ab786f78f6938b11a3@gmail.com"},"message":"[IR] Rename the class templates for the case iterator and case handle to\nnot collide with the naming convention for template *arguments*. In at\nleast one case they actually collided and this confuses MSVC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300038 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/76dc6181d8cbdfa21e8aad36a20c06210a322fd4"},{"sha":"2b0a45f335f6aa2cd398be07692b254fb78baacb","author":{"name":"George Rimar","email":"4f1e9f067cb1f528bdd5c61b67a67d4a3f7472a3@accesssoftek.com"},"message":"[DWARF] - Refactoring of DWARFContextInMemory implementation.\n\nThis change is basically relative to D31136, where I initially wanted to\nimplement some relocations handling optimization which shows it can give\nsignificant boost. Though even without any caching algorithm looks\ncode can have some cleanup at first.\n\nRefactoring separates out code for taking symbol address, used in relocations\ncomputation.\n\nDifferential revision: https://reviews.llvm.org/D31747\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300039 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/2b0a45f335f6aa2cd398be07692b254fb78baacb"},{"sha":"9a421935fb7bf056fa931f25c9cf35f73dfc3c8d","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"[AMDGPU] SDWA: make pass global\n\nSummary: Remove checks for basic blocks.\n\nReviewers: vpykhtin, rampitec, arsenm\n\nSubscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye\n\nDifferential Revision: https://reviews.llvm.org/D31935\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300040 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/9a421935fb7bf056fa931f25c9cf35f73dfc3c8d"},{"sha":"715890b2794cb3c91a3745bf2630441340ea1dd6","author":{"name":"Piotr Padlewski","email":"fb20fa40ab7fd28be20690983960497132f54779@gmail.com"},"message":"[LangRef] fix documentation\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300050 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/715890b2794cb3c91a3745bf2630441340ea1dd6"},{"sha":"6120b8f9e92893a9ab8840cc4e7a154c37323079","author":{"name":"Krasimir Georgiev","email":"3fcda06dab6c1cae8afe14f563d9e144a7f8ccee@google.com"},"message":"[DWARF] Fix compiler warnings in DWARFContext.cpp, NFCi\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300051 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/6120b8f9e92893a9ab8840cc4e7a154c37323079"},{"sha":"c33bdfa7b1fdb46d0ba5701593ebd1e20759bc4a","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[SystemZ]  TargetTransformInfo cost functions implemented.\n\ngetArithmeticInstrCost(), getShuffleCost(), getCastInstrCost(),\ngetCmpSelInstrCost(), getVectorInstrCost(), getMemoryOpCost(),\ngetInterleavedMemoryOpCost() implemented.\n\nInterleaved access vectorization enabled.\n\nBasicTTIImpl::getCastInstrCost() improved to check for legal extending loads,\nin which case the cost of the z/sext instruction becomes 0.\n\nReview: Ulrich Weigand, Renato Golin.\nhttps://reviews.llvm.org/D29631\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300052 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/c33bdfa7b1fdb46d0ba5701593ebd1e20759bc4a"},{"sha":"2778098e17684af9caee33336b2e4f84c6e493c5","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[SystemZ]  Updated test fp-cast.ll\n\nThis did not get included in the previous commit for SystemZ cost functions.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300053 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/2778098e17684af9caee33336b2e4f84c6e493c5"},{"sha":"fcce15e390223db902944aa7c629ef66f53f09c8","author":{"name":"Dmitry Preobrazhensky","email":"2fff238649643f8ccf6388213f9658c9bab72388@amd.com"},"message":"[AMDGPU][MC] Corrected src0 size for s_cbranch_join\n\nFix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159\n\nReviewers: vpykhtin, arsenm\n\nDifferential Revision: https://reviews.llvm.org/D31595\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300055 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/fcce15e390223db902944aa7c629ef66f53f09c8"},{"sha":"43d439da886fb7df1b90c1d8136c58de47e24b92","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[LoopVectorizer, TTI]  New method supportsEfficientVectorElementLoadStore()\n\nSince SystemZ supports vector element load/store instructions, there is no\nneed for extracts/inserts if a vector load/store gets scalarized.\n\nThis patch lets Target specify that it supports such instructions by means of\na new TTI hook that defaults to false.\n\nThe use for this is in the LoopVectorizer getScalarizationOverhead() method,\nwhich will with this patch produce a smaller sum for a vector load/store on\nSystemZ.\n\nNew test: test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll\n\nReview: Adam Nemet\nhttps://reviews.llvm.org/D30680\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300056 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/43d439da886fb7df1b90c1d8136c58de47e24b92"},{"sha":"e353fb8d83b1608e9ea428d09c5e497b2b8b233e","author":{"name":"Igor Breger","email":"c5b47ab787d3dab9b5464f985bbfbd60519fce52@intel.com"},"message":"[GlobalIsel][X86] support G_CONSTANT selection.\n\nSummary: [GlobalISel][X86] support G_CONSTANT selection. Add regbank select tests.\n\nReviewers: zvi, guyblank\n\nReviewed By: guyblank\n\nSubscribers: llvm-commits, dberris, rovka, kristof.beyls\n\nDifferential Revision: https://reviews.llvm.org/D31974\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300057 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/e353fb8d83b1608e9ea428d09c5e497b2b8b233e"},{"sha":"16b23e95d589563d5eda818b9e76e67771a08960","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[LoopVectorizer]  Improve handling of branches during cost estimation.\n\nThe cost for a branch after vectorization is very different depending on if\nthe vectorizer will if-convert the block (branch is eliminated), or if\nscalarized and predicated blocks will be produced (branch duplicated before\neach block). There is also the case of remaining scalar branches, such as the\nback-edge branch.\n\nThis patch handles these cases differently with TTI based cost estimates.\n\nReview: Matthew Simpson\nhttps://reviews.llvm.org/D31175\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300058 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/16b23e95d589563d5eda818b9e76e67771a08960"}]}
{"actor":{"display_login":"kzhuravl"}}