{"push_id":1912712410,"size":1,"distinct_size":1,"ref":"refs/heads/RISC-V","head":"54d5af6765c1611aa39bd08a5adeb799afd25412","before":"70964e8652b6825c248c974becabd94f77ac1412","commits":[{"sha":"54d5af6765c1611aa39bd08a5adeb799afd25412","author":{"name":"Brandon Perez","email":"8846dccadd1e5e98643d1743d2513f40f720a9f2@alumni.cmu.edu"},"message":"Changed the names for the 447 variables in the Makefile.\n\nThis matches how the Verilog starter code's Makefile names these\nvariables.","distinct":true,"url":"https://api.github.com/repos/CMU-18447/simulator_starter_code/commits/54d5af6765c1611aa39bd08a5adeb799afd25412"}]}
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