{"push_id":1614409252,"size":17,"distinct_size":17,"ref":"refs/heads/p9-cas","head":"ed7c7baa129d7ae1b173fb9c3adf7e078fcd9787","before":"87e11198a8c4b2718b5b05f4655c02c3f78e51b0","commits":[{"sha":"0e6ae69e69a384514c9aa947457557e67bfea816","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"spapr: Add ibm,processor-radix-AP-encodings to the device tree\n\nUse the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU\ninformation from KVM and present the page encodings in the device tree\nunder ibm,processor-radix-AP-encodings. This provides page size\ninformation to the guest which is necessary for it to use radix mode.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/0e6ae69e69a384514c9aa947457557e67bfea816"},{"sha":"fba1f87879dd08c1a64ddedbf8fd5b6bcaa1b2ee","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3\n\nQuery and cache the value of two new KVM capabilities that indicate\nKVM's support for new radix and hash modes of the MMU.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/fba1f87879dd08c1a64ddedbf8fd5b6bcaa1b2ee"},{"sha":"32628339ff5746cfb07886c20658ab49adf84259","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"spapr: Only setup HPT if necessary.\n\nIf QEMU is using KVM, and KVM is capable of running in radix mode,\nguests can be run in real-mode without allocating a HPT (because KVM\nwill use a minimal RPT). So in this case, we avoid creating the HPT\nat reset time and later (during CAS) create it if it is necessary.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/32628339ff5746cfb07886c20658ab49adf84259"},{"sha":"8d515d0e2b3da9f413c1ac2abd507d336e3ed693","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Add new H-CALL shells for in memory table translation\n\nThe use of the new in memory tables introduced in ISAv3.00 for translation,\nalso referred to as process tables, requires the introduction of 3 new\nH-CALLs; H_REGISTER_PROCESS_TABLE, H_CLEAN_SLB, and H_INVALIDATE_PID.\n\nAdd shells for each of these and register them as the hypercall handlers.\nCurrently they all log an unimplemented hypercall and return H_FUNCTION.\n\nSigned-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/8d515d0e2b3da9f413c1ac2abd507d336e3ed693"},{"sha":"92438364653abc6b732b817e3fc0a42a1dfb8360","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL\n\nThe H_REGISTER_PROCESS_TABLE H_CALL is used by a guest to indicate to the\nhypervisor where in memory its process table is and how translation should\nbe performed using this process table.\n\nProvide the implementation of this H_CALL for a guest.\n\nWe first check for invalid flags, then parse the flags to determine the\noperation, and then check the other parameters for valid values based on\nthe operation (register new table/deregister table/maintain registration).\nThe process table is then stored in the appropriate location and registered\nwith the hypervisor (if running under KVM), and the LPCR_[UPRT/GTSE] bits\nare updated as required.\n\nSigned-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/92438364653abc6b732b817e3fc0a42a1dfb8360"},{"sha":"1bb05dde5211c21c2a33c045815d5ce535deb8ff","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"spapr: move spapr_populate_pa_features()\n\nIn the next patch, spapr_fixup_cpu_dt() will need to call\nspapr_populate_pa_features() so move it's definition up without making\nany other changes.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/1bb05dde5211c21c2a33c045815d5ce535deb8ff"},{"sha":"51a8ee2a65e5b2e7d6247d994700d962e554c062","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"spapr: Enable ISA 3.0 MMU mode selection via CAS\n\nAdd the new node, /chosen/ibm,arch-vec-5-platform-support to the\ndevice tree. This allows the guest to determine which modes are\nsupported by the hypervisor.\n\nUpdate the option vector processing in h_client_architecture_support()\nto handle the new MMU bits. This allows guests to request hash or\nradix mode and QEMU to create the guest's HPT at this time if it is\nnecessary but hasn't yet been done.  QEMU will terminate the guest if\nit requests an unavailable mode, as required by the architecture.\n\nExtend the ibm,pa-features node with the new ISA 3.0 values\nand set the radix bit if KVM supports radix mode. This probably won't\nbe used directly by guests to determine the availability of radix mode\n(that is indicated by the new node added above) but the architecture\nrequires that it be set when the hardware supports it.\n\nISA 3.0 guests will now begin to call h_register_process_table(),\nwhich has been added previously.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/51a8ee2a65e5b2e7d6247d994700d962e554c062"},{"sha":"8c337f7b7cd3fc8e20eabafac3fe6acf6708d55c","author":{"name":"Sam Bobroff","email":"198d89b753a45ced78bccd32615a2bcbd2522272@au1.ibm.com"},"message":"spapr: Workaround for broken radix guests\n\nFor a little while around 4.9, Linux kernels that saw the radix bit in\nibm,pa-features would attempt to set up the MMU as if they were a\nhypervisor, even if they were a guest, which would cause them to\ncrash.\n\nWork around this by detecting pre-ISA 3.0 guests by their lack of that\nbit in option vector 1, and then removing the radix bit from\nibm,pa-features. Note: This now requires regeneration of that node\nafter CAS negotiation.\n\nSigned-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/8c337f7b7cd3fc8e20eabafac3fe6acf6708d55c"},{"sha":"763f3a36de46a9760bea86b58ecc7c96ec2eb622","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Add POWER9/ISAv3.00 to compat_table\n\ncompat_table contains the list of logical pvr compat modes which a cpu can\noperate in. It is a list of struct CompatInfo which contains the given pvr\nvalue for a compat mode, the pcr bits which should be set to operate in\nthat compat mode, the pcr level which must be present in pcr_supported for\na processor to support that compat mode and the max threads possible in\nthat compat mode.\n\nAdd an entry for the POWER9/ISAv3.00 logical pvr which represents a\nprocessor running with support for logical pvr 0x0f000005. A processor\nrunning in this mode should have PCR_COMPAT_3_00 set in the pcr (if\navailable in pcr_mask) and should have PCR_COMPAT_3_00 in pcr_supported\nto indicate that it is capable of running in this compat mode.\n\nAlso add PCR_COMPAT_3_00 to the bits which must be set for all previous\ncompat modes. Since no processor models contain this bit yet in pcr_mask\nit will never be set, but this ensures we don't forget to in the future.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/763f3a36de46a9760bea86b58ecc7c96ec2eb622"},{"sha":"55daa815876f23b8bb1043b07b7fb37413a4f440","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Add Instruction Authority Mask Register Check\n\nThe instruction authority mask register (IAMR) can be used to restrict\npermissions for instruction fetch accesses on a per key basis for each\nof 32 different key values. Access permissions are derived based on the\nspecific key value stored in the relevant page table entry.\n\nThe IAMR was introduced in, and is present in processors since, POWER8\n(ISA v2.07). Thus introduce a function to check access permissions based\non the pte key value and the contents of the IAMR when handling a page\nfault to ensure sufficient access permissions for an instruction fetch.\n\nA hash pte contains a key value in bits 2:3|52:54 of the second double word\nof the pte, this key value gives an index into the IAMR which contains 32\n2-bit access masks. If the least significant bit of the 2-bit access mask\ncorresponding to the given key value is set (IAMR[key] & 0x1 == 0x1) then\nthe instruction fetch is not permitted and an ISI is generated accordingly.\nWhile we're here, add defines for the srr1 bits to be set for the ISI for\nclarity.\n\ne.g.\n\npte:\ndw0 [XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]\ndw1 [XX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXXX]\n       ^^                                                ^^^\nkey = 01010 (0x0a)\n\nIAMR: [XXXXXXXXXXXXXXXXXXXX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]\n                           ^^\nAccess mask = 0b01\n\nTest access mask: 0b01 & 0x1 == 0x1\n\nLeast significant bit of the access mask is set, thus the instruction fetch\nis not permitted. We should generate an instruction storage interrupt (ISI)\nwith bit 42 of SRR1 set to indicate access precluded by virtual page class\nkey protection.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/55daa815876f23b8bb1043b07b7fb37413a4f440"},{"sha":"f95c5d5176b4a14878875682750e1e846fa2c147","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Add execute permission checking to access authority check\n\nBasic storage protection defines various access authority permissions\nbased on a slb storage key and pte pp value pair. This access authority\ndefines read, write and execute permissions however currently we only\nuse this to control read and write permissions and ignore the execute\ncontrol.\n\nFix the code to allow execute permissions based on the key-pp value pair.\nExecute is allowed under the same conditions which enable reads.\n(i.e. read permission -> execute permission)","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/f95c5d5176b4a14878875682750e1e846fa2c147"},{"sha":"f36d6756d79d8b4b12964d875a0aa59b5339a4ed","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Move no-execute and guarded page checking into new function\n\nA pte entry has bit fields which can be used to make a page no-execute or\nguarded, if either of these bits are set then an instruction access to this\npage will fail. Currently these bits are checked with the pp_prot function\nhowever the ISA specifies that the access authority controlled by the\nkey-pp value pair should only be checked on an instruction access after\nthe no-execute and guard bits have already been verified to permit the\naccess.\n\nMove the no-execute and guard bit checking into a new separate function.\nNote that we can remove the check for the no-execute bit in the slb entry\nsince this check was already performed above when we obtained the slb\nentry.\n\nIn the event that the no-execute or guard bits are set, an ISI should be\ngenerated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a\ndefine for this for clarity.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/f36d6756d79d8b4b12964d875a0aa59b5339a4ed"},{"sha":"c5222ea8fb8e5f770db9c4a96f1df13445d32490","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Rework hash mmu page fault code and add defines for clarity\n\nThe hash mmu page fault handling code is responsible for generating ISIs\nand DSIs when access permissions cause an access to fail. Part of this\ninvolves setting the srr1 or dsisr registers to indicate what causes the\naccess to fail. Add defines for the bit fields of these registers and\nrework the code to use these new defines in order to improve readability\nand code clarity.\n\nWhile we're here, update what is logged when an access fails to include\ninformation as to what caused to access to fail for debug purposes.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/c5222ea8fb8e5f770db9c4a96f1df13445d32490"},{"sha":"d7aa4d4a95fc49d4529e05c532eba0955fe5af58","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Add ibm,processor-radix-AP-encodings for TCG\n\nThe ibm,processor-radix-AP-encodings device tree property of the cpu node\nis used to specify the radix mode supported page sizes of the processor\nto the guest os. Contained in the top 3 bits of the msb is the actual\npage size (AP) encoding associated with the corresponding radix mode\nsupported page size. Add this property for a TCG guest, note the TCG code\nis capable of translating any format so just add the 4 default page sizes.\n\nThe ibm,processor-radix-AP-encodings device tree property is defined as:\nOne to n cells in ascending order of radix mode supported page sizes\nencoded as BE ints (32bit on ppc) in the form:\n0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy\n- 0bxxx -> AP encoding\n- 0byyyyyyyyyyyyyyyyyyyyyyyyyyyyy -> supported page size encoded as a shift","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/d7aa4d4a95fc49d4529e05c532eba0955fe5af58"},{"sha":"002f1b34ba2789e4dda6dd61fe73b1e94852d5a0","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Flush TLB on write to PIDR\n\nThe PIDR (process id register) is used to store the id of the currently\nrunning process, which is used to select the process table entry used to\nperform address translation. This means that when we write to this register\nall the translations in the TLB become outdated as they are for a\npreviously running process. Thus when this register is written to we need\nto invalidate the TLB entries to ensure stale entries aren't used to\nto perform translation for the new process, which would result in at best\nsegfaults or alternatively just random memory being accessed.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/002f1b34ba2789e4dda6dd61fe73b1e94852d5a0"},{"sha":"b0b51df8cc844c0f0d7bc8764b9793d2959e68c2","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Adapt tlbie[l] for ISAv3.00 Support\n\nThe tlbie[l] instructions are used to invalidate TLB entries used to cache\naddress translations.\n\nISAv3.00 changes these instructions to take additional arguments to change\nthe behaviour of the instruction which allow the caller to limit what is\ninvalidated. Since the majority of things which a real POWER9 processor\nwill cache aren't cached in QEMU for tcg, in fact the only thing QEMU\nactually caches is the effective to real address translation (or the ERAT),\nwe don't actually really care about these new instruction argument fields.\n\nSo adapt the handler gen functions to accept the new instuction argument\nfields so an illegal instruction exception isn't raised when they are\ncalled. Note that we ignore the new arguments anyway and simply call the\nsame handlers as before, this is fine since they just invalidate the entire\nTLB anyway which is the only translation related cache which QEMU keeps.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/b0b51df8cc844c0f0d7bc8764b9793d2959e68c2"},{"sha":"ed7c7baa129d7ae1b173fb9c3adf7e078fcd9787","author":{"name":"Suraj Jitindar Singh","email":"cb180b40825a3729ef70b8cfaa9014c5711527dc@gmail.com"},"message":"target/ppc: Implement ISA V3.00 radix page fault handler\n\nISA V3.00 introduced a new radix mmu model. Implement the page fault\nhandler for this so we can run a tcg guest in radix mode and perform\naddress translation correctly.\n\nIn real mode (mmu turned off) addresses are masked to remove the top\n4 bits and then are subject to partition scoped translation, since we only\nsupport pseries at this stage it is only necessary to perform the masking\nand then we're done.\n\nIn virtual mode (mmu turned on) address translation if performed as\nfollows:\n\n1. Use the quadrant to determine the fully qualified address.\n\nThe fully qualified address is defined as the combination of the effective\naddress, the effective logical partition id (LPID) and the effective\nprocess id (PID). Based on the quadrant (EA63:62) we set the pid and lpid\nlike so:\n\nquadrant 0: lpid = LPIDR, pid = PIDR\nquadrant 1: HV only (not allowed in pseries)\nquadrant 2: HV only (not allowed in pseries)\nquadrant 3: lpid = LPIDR, pid = 0\n\nIf we can't get the fully qualified address we raise a segment interrupt.\n\n2. Find the guest radix tree\n\nWe ask the virtual hypervisor for the partition table which was registered\nwith H_REGISTER_PROC_TBL which points us to the process table in guest\nmemory. We then index this table by pid to get the process table entry\nwhich points us to the appropriate radix tree to translate the address.\n\nIf the process table isn't big enough to contain an entry for the current\npid then we raise a storage interrupt.\n\n3. Walk the radix tree\n\nNext we walk the radix tree where each level is a table of page directory\nentries indexed by some number of bits from the effective address, where\nthe number of bits is determined by the table size. We continue to walk\nthe tree (while entries are valid and the table is of minimum size) until\nwe reach a table of page table entries, indicated by having the leaf bit\nset. The appropriate pte is then checked for sufficient access permissions,\nthe reference and change bits are updated and the real address is\ncalculated from the real page number bits of the pte and the low bits of\nthe effective address.\n\nIf we can't find an entry or can't access the entry bacause of permissions\nthen we raise a storage interrupt.\n\nSince we now have radix support, we can add this bit to pa-features to\ncommunicate this to the guest.","distinct":true,"url":"https://api.github.com/repos/sambltc/qemu/commits/ed7c7baa129d7ae1b173fb9c3adf7e078fcd9787"}]}
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