{"push_id":1906688567,"size":2,"distinct_size":1,"ref":"refs/heads/aliases","head":"50a655ade9d174c8ae60362071eaf0918badf4fe","before":"a4a6d94966b8dbc676e8f27873a349bf517760e3","commits":[{"sha":"e0d921fd915024d90d2233cb4613d07890c81ca5","author":{"name":"Palmer Dabbelt","email":"da5bafab56f66b7236a8991f0e01aad56ae901eb@dabbelt.com"},"message":"(WIP) RISC-V: Provide better disassembly of alignment sequences\n\nOur assembler now almost always inserts alignment sequences that result\nin invalid instruction sequences, which the linker will then relax away.\nThis patch detects those sequences and marks them as R_RISCV_ALIGN when\ndisassembling.\n\nBefore this patch, this sequence\n\n    addi x31, x15, 1\n    .align 2\n    li x0, 19\n\ndoesn't disassemble correctly\n\n    0:   00178f93                addi    t6,a5,1\n    4:   0100                    addi    s0,sp,128\n    6:   1300                    addi    s0,sp,416\n    8:   3000                    fld     fs0,32(s0)\n    a:   0001                    nop\n\nbut with the patch it does\n\n    0:   00178f93                addi    t6,a5,1\n    4:   00 01 00                        # R_RISCV_ALIGN\n                         4: R_RISCV_ALIGN        *ABS*+0x3\n    7:   01300013                li      zero,19","distinct":false,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/e0d921fd915024d90d2233cb4613d07890c81ca5"},{"sha":"50a655ade9d174c8ae60362071eaf0918badf4fe","author":{"name":"Palmer Dabbelt","email":"da5bafab56f66b7236a8991f0e01aad56ae901eb@dabbelt.com"},"message":"RISC-V: Mark \"c.nop\" as an alias\n\nThis fixes \"-M noaliases\" disassembly for \"c.nop\", which is an alias for\n\"c.addi x0, 0\".\n\nopcodes/ChangeLog\n\n2017-08-01  Palmer Dabbelt  <palmer@dabbelt.com>\n\n        * riscv-opc.c (riscv_opcodes): Mark \"c.nop\" as an alias.","distinct":true,"url":"https://api.github.com/repos/riscv/riscv-binutils-gdb/commits/50a655ade9d174c8ae60362071eaf0918badf4fe"}]}
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