{"push_id":1845249741,"size":59,"distinct_size":59,"ref":"refs/heads/testing","head":"d1a4d8843cbbb2f6a93ea677ab69a81b3d753cda","before":"3fababf4049c209e92c76b6dd69c6f52653c5c25","commits":[{"sha":"9c2e2cab9ad9169e337cf397fbed3bafbbb72b74","author":{"name":"Jaehoon Chung","email":"08ff0d27dcc0f9354ed3c8ec20af4f687d9895da@samsung.com"},"message":"ARM: dts: exynos4: change the nodes relevant to mmc/sd\n\nChange the nodes relevant to mmc/sd for using DM.\ncompatible are also changed to each SoCs.\n\nSigned-off-by: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Minkyu Kang <mk7.kang@samsung.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/9c2e2cab9ad9169e337cf397fbed3bafbbb72b74"},{"sha":"7f3a40cf98f140fd63386d45d6df588aa084137c","author":{"name":"Jaehoon Chung","email":"08ff0d27dcc0f9354ed3c8ec20af4f687d9895da@samsung.com"},"message":"configs: enable the CONFIG_DM_MMC for exynos4 series\n\nEnable the CONFIG_DM_MMC for exynos4 series.\n\nSigned-off-by: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Minkyu Kang <mk7.kang@samsung.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/7f3a40cf98f140fd63386d45d6df588aa084137c"},{"sha":"c9972a8652d8631bbd907a12b9b6c84a33a5a0f9","author":{"name":"Jaehoon Chung","email":"08ff0d27dcc0f9354ed3c8ec20af4f687d9895da@samsung.com"},"message":"ARM: dts: exynos5422-odroidxu3: add the LDO's nodes\n\nAdd the LDO's nodes that taken from Linux Kernel.\n\nSigned-off-by: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Minkyu Kang <mk7.kang@samsung.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/c9972a8652d8631bbd907a12b9b6c84a33a5a0f9"},{"sha":"df494d8001daedf07cd61e8630dd0aac2ccd5c1d","author":{"name":"Jaehoon Chung","email":"08ff0d27dcc0f9354ed3c8ec20af4f687d9895da@samsung.com"},"message":"configs: odroid-xu3: remove the CONFIG_I2C_COMPAT\n\nRemove the CONFIG_I2C_COMPAT, instead enable the CONFIG_SYS_I2C_S3C24X0.\n\nSigned-off-by: Jaehoon Chung <jh80.chung@samsung.com>\nSigned-off-by: Minkyu Kang <mk7.kang@samsung.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/df494d8001daedf07cd61e8630dd0aac2ccd5c1d"},{"sha":"b0174c39b336adc5044d2ca044d6d5e67ca0e879","author":{"name":"Jagan Teki","email":"bf50983bb3c3c45d25cbb5e6052c6eba4553f727@amarulasolutions.com"},"message":"sun8i: h3: Add initial NanoPi M1 Plus support\n\nNanoPi M1 Plus is designed and developed by FriendlyElec\nfor professionals, enterprise users, makers and hobbyists\nusing the Allwinner H3 SOC.\n\nNanoPi M1 Plus key features\n- Allwinner H3, Quad-core Cortex-A7@1.2GHz\n- 1GB DDR3 RAM\n- 8GB eMMC\n- microSD slot\n- 10/100/1000M Ethernet\n- Serial Debug Port\n- 5V 2A DC power-supply\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/b0174c39b336adc5044d2ca044d6d5e67ca0e879"},{"sha":"9934aba42748e413646fb60b4f762422415437a7","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: makes an invisible option for H3-like DRAM controllers\n\nAllwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like\nDesignWare DRAM controller, which do not have official free DRAM\ninitialization code, but can use modified dram_sun8i_h3.c.\n\nAdd a invisible option for easier DRAM initialization code reuse.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nAcked-by: Maxime Ripard <maxime.ripard@free-electrons.com>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/9934aba42748e413646fb60b4f762422415437a7"},{"sha":"f43a009959e6c1f1ace8b76ef525651ac4729c9d","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: Rename bus-width related macros in H3 DRAM code\n\nThe DesignWare DRAM controller used by H3 and newer SoCs use a bit to\nidentify whether the DRAM is half-width.\n\nAs H3 itself come with 32-bit DRAM, the two modes of the bit used to be\nnamed \"MCTL_CR_32BIT\" and \"MCTL_CR_16BIT\", but for SoCs with 16-bit DRAM\nthey're really 8-bit and 16-bit.\n\nRename the bit's macro, and also rename the variable name in\ndram_sun8i_h3.c.\n\nThis commit do not add 16-bit DRAM controller support, but the support\nwill be introduced in next commit.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/f43a009959e6c1f1ace8b76ef525651ac4729c9d"},{"sha":"87098d701da77f264c9cbed67a5d6fb27fbaaf3f","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add option for 16-bit DW DRAM controller\n\nSome Allwinner SoCs features a DesignWare-like controller with only 16\nbit bus width.\n\nAdd support for them.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/87098d701da77f264c9cbed67a5d6fb27fbaaf3f"},{"sha":"66b12526f0bdfb284a5152cd31d5eed849e7b873","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add bank detection code to H3 DRAM initialization code\n\nSome DDR2 DRAM have only four banks, not eight.\n\nAdd code to detect this situation.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/66b12526f0bdfb284a5152cd31d5eed849e7b873"},{"sha":"f6457ce5789b885706a2877edb70b5f8e61cf075","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: Add selective DRAM type and timing\n\nDRAM chip varies, and one code cannot satisfy all DRAMs.\n\nAdd options to select a timing set.\n\nCurrently only DDR3-1333 (the original set) is added into it.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/f6457ce5789b885706a2877edb70b5f8e61cf075"},{"sha":"176868bc65c15f10e585209af69bca93a0d18a69","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: enable dual rank detection in DesignWare-like DRAM code\n\nThe DesignWare-like DRAM code used to set the controller defaultly to\nsingle rank mode, which makes it not able to detect the second rank.\n\nSet the default value to dual rank, thus the rank detection code can\nwork and finally the rank setting will be the correct value.\n\nCurrently we know little about the dual-rank on R40, and the usage\nof A15 address line seems to be breaking dual-rank support. The only R40\nboard currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather\nthan dual-rank, thus we cannot do research for it. So dual rank detection\nis temporarily disabled on R40.\n\nThis change is tested on a Orange Pi One (H3, single rank), a Pine64+\n2GiB version (A64, single rank) , a Pinebook early prototype with DDR3\n(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins\non one chip).\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/176868bc65c15f10e585209af69bca93a0d18a69"},{"sha":"67337e68a5a88ecbe4ae0df6a91c653f2817c3e1","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add support for the DDR2 in V3s SoC\n\nAllwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its\ntiming param.\n\nAdd support for it.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nAcked-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/67337e68a5a88ecbe4ae0df6a91c653f2817c3e1"},{"sha":"3ec0698b8a5bf29d5b35f5057a09be348b067a1a","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add support for V3s DRAM controller\n\nAllwinner V3s features a DRAM controller like the on in H3, but with a\nDDR2 DRAM.\n\nAdd support for it.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/3ec0698b8a5bf29d5b35f5057a09be348b067a1a"},{"sha":"7d06e59f73f0d4d2733fe41529cefa264404e0d9","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.io"},"message":"sunxi: enable DRAM initialization and SPL for V3s SoC\n\nAs we have already support for the DesignWare DRAM controller and the\nintegrated DDR2 chip of V3s, let's enable the SPL support for V3s.\n\nThis patch also contains the default DRAM configuration for V3s.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.io>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/7d06e59f73f0d4d2733fe41529cefa264404e0d9"},{"sha":"72cc987002539b23b0c97321cc2ccfc1b05f48de","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller\n\nSome A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM\nchips.\n\nAdd support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.\n\nReal LPDDR3 chips' support is not added yet in this commit.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/72cc987002539b23b0c97321cc2ccfc1b05f48de"},{"sha":"ec4670a13722a14bdeed355465a55b2f93831af2","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"sunxi: add LPDDR3 timing from stock boot0\n\nAs we added LPDDR3 support in the former patch, we need a set of timing\ninfo to really enable it.\n\nAdd the timing info used by stock boot0.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nAcked-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/ec4670a13722a14bdeed355465a55b2f93831af2"},{"sha":"84580628b8e11c299d9a3f6b35c7ef917ab31290","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.io"},"message":"sunxi: add a defconfig for SoPine w/ official baseboard\n\nThe SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM\nchip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card\ndetect pin of the MicroSD slot is broken, however, it doesn't matter as\nthe design of SoPine didn't allow hot-swapping the MicroSD card (The\nMicroSD slot is at the back of the SoM, and when the SoM is installed on\nthe baseboard, it's nearly impossible to remove the MicroSD).\n\nThe official baseboard of it is a board with nearly the same connectors\nwith the original Pine64+, with the MicroUSB power jack replaced, and\nat the position of MicroSD slot a eMMC module slot is added.\n\nAdd support for SoPine with the official baseboard by adding its\ndefconfig file. It still uses the device tree of Pine64, however, it\nwill change after a proper device tree of SoPine with baseboard is\naccepted by Linux mainline.\n\nSigned-off-by: Icenowy Zheng <icenowy@aosc.io>\n[Update board/sunxi/MAINTAINERS]\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/84580628b8e11c299d9a3f6b35c7ef917ab31290"},{"sha":"3474827294ca188446c8e52decd81a0908fd65e2","author":{"name":"Chen-Yu Tsai","email":"d935d34b7d281e4f50030b838a1bf5c8f10bdb43@csie.org"},"message":"sunxi: psci: Move entry address setting to separate function\n\nCurrently we set the entry address in the psci_cpu_on function.\nHowever R40 has a different register for this. This resulted in\nan #ifdef / #else block in psci_cpu_on, which we avoided having\nin the first place.\n\nMove this part into a separate function, defined differently for\nthe R40 as opposed to the other single cluster platforms.\n\nSigned-off-by: Chen-Yu Tsai <wens@csie.org>\nAcked-by: Maxime Ripard <maxime.ripard@free-electrons.com>\nReviewed-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/3474827294ca188446c8e52decd81a0908fd65e2"},{"sha":"d6b1d7d81ba71dfdca84a7e38e334b73d3732fc0","author":{"name":"Jagan Teki","email":"bf50983bb3c3c45d25cbb5e6052c6eba4553f727@amarulasolutions.com"},"message":"sun50i: h5: Add initial Orangepi Zero Plus 2 support\n\nOrangepi Zero Plus 2 is an open-source single-board computer\nusing the Allwinner h5 SOC.\n\nH5 Orangepi Zero Plus 2 has\n- Quad-core Cortex-A53\n- 512MB DDR3\n- micrSD slot and 8GB eMMC\n- Debug TTL UART\n- HDMI\n- Wifi + BT\n- OTG+power supply\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/d6b1d7d81ba71dfdca84a7e38e334b73d3732fc0"},{"sha":"bdf9577355b0efcf5a27a4fdef344a5b8b70f9f2","author":{"name":"Jagan Teki","email":"bf50983bb3c3c45d25cbb5e6052c6eba4553f727@amarulasolutions.com"},"message":"sun50i: a64: Add initial Orangepi Win/WinPlus support\n\nOrangepi Win/WinPlus is an open-source single-board computer\nusing the Allwinner A64 SOC.\n\nA64 Orangepi Win/WinPlus has\n- A64 Quad-core Cortex-A53 64bit\n- 1GB(Win)/2GB(Win Plus) DDR3 SDRAM\n- Debug TTL UART\n- Four USB 2.0\n- HDMI\n- LCD\n- Audio and MIC\n- Wifi + BT\n- IR receiver\n- 5V DC power supply\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nTested-by: Jagan Teki <jagan@amarulasolutions.com>","distinct":true,"url":"https://api.github.com/repos/lmajewski/u-boot-dfu/commits/bdf9577355b0efcf5a27a4fdef344a5b8b70f9f2"}]}
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