{"push_id":1781922200,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"87a5665e4312ee84d473b090da956fd33816ced8","before":"274d908d98617f928e47b192cc2f68a3f7ded512","commits":[{"sha":"87a5665e4312ee84d473b090da956fd33816ced8","author":{"name":"Wesley W. Terpstra","email":"335c2d428a69ab96434ed404eadfac51b77392e1@sifive.com"},"message":"axi4: only block writes if SAME master has outstanding reads (#782)\n\n* axi4: only block writes if SAME master has outstanding reads\r\n* tilelink2: ToAXI4 rename variable\r\nTL uses sources, not IDs like AXI. Keep it less confusing.\r\n* tilelink2: ToAXI4 improve stall circuit delay\r\nDon't bother decoding the AXI ID to compute stall.","distinct":true,"url":"https://api.github.com/repos/freechipsproject/rocket-chip/commits/87a5665e4312ee84d473b090da956fd33816ced8"}]}
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