{"push_id":1952531130,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"a27ff549ae450f87cdc0887dc4989078cdd27cfc","before":"6f1518f1c5d708e7eff51d3b3c374bf17fb2acff","commits":[{"sha":"a27ff549ae450f87cdc0887dc4989078cdd27cfc","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@intel.com"},"message":"[X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as well\n\nCurrently we start applying this on Haswell and newer. I don't believe anything changed in the Haswell architecture to make this the right cutoff point. The partial flag handling around this has been roughly the same since Sandybridge.\n\nDifferential Revision: https://reviews.llvm.org/D37250","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/a27ff549ae450f87cdc0887dc4989078cdd27cfc"}]}
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