{"push_id":1866112245,"size":22,"distinct_size":22,"ref":"refs/heads/upstream-master","head":"ed6458726a9d987f5466f7b92469085d2a2d3685","before":"a778cd5610b40eec037417565671d2717bc49def","commits":[{"sha":"d9a7b125d6b8048a503d10117ee8b7cbc44cc889","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"qdev-properties.h: Explicitly set the default value for arraylen properties\n\nIn DEFINE_PROP_ARRAY, because we use a PropertyInfo (qdev_prop_arraylen)\nwhich has a .set_default_value member we will set the field to a default\nvalue. That default value will be zero, by the C rule that struct\ninitialization sets unmentioned members to zero if at least one member\nis initialized. However it's clearer to state it explicitly.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>\nMessage-id: 1499788408-10096-2-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/d9a7b125d6b8048a503d10117ee8b7cbc44cc889"},{"sha":"5cc56cc6872122af318f07088b7d599c3781719f","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"qdev: support properties which don't set a default value\n\nIn some situations it's useful to have a qdev property which doesn't\nautomatically set its default value when qdev_property_add_static is\ncalled (for instance when the default value is not constant).\n\nSupport this by adding a flag to the Property struct indicating\nwhether to set the default value.  This replaces the existing test\nfor whether the PropertyInfo set_default_value function pointer is\nNULL, and we set the .set_default field to true for all those cases\nof struct Property which use a PropertyInfo with a non-NULL\nset_default_value, so behaviour remains the same as before.\n\nThis gives us the semantics of:\n * if .set_default is true, then .info->set_default_value must\n   be not NULL, and .defval is used as the the default value of\n   the property\n * otherwise, the property system does not set any default, and\n   the field will retain whatever initial value it was given by\n   the device's .instance_init method\n\nWe define two new macros DEFINE_PROP_SIGNED_NODEFAULT and\nDEFINE_PROP_UNSIGNED_NODEFAULT, to cover the most plausible use cases\nof wanting to set an integer property with no default value.\n\nSuggested-by: Markus Armbruster <armbru@redhat.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>\nReviewed-by: Markus Armbruster <armbru@redhat.com>\nMessage-id: 1499788408-10096-3-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/5cc56cc6872122af318f07088b7d599c3781719f"},{"sha":"8d92e26b452f8961ec90df3f93cf5f3b7a9d158f","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions\n\nThe Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't\na configurable option for the hardware).  Make the default value of\nthe pmsav7-dregion property be set per-cpu, so we don't need to have\nevery user of these CPUs set it manually.  (The existing default of\n16 is correct for the other PMSAv7 core, the Cortex-R5.)\n\nThis fixes a bug where we were creating the M3 and M4 with\ntoo many regions; most guest software would not notice or\ncare, though, since it would just not use the registers\nassociated with the unexpected extra regions.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>\nMessage-id: 1499788408-10096-4-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/8d92e26b452f8961ec90df3f93cf5f3b7a9d158f"},{"sha":"df0311e634828fdc99ca59352aef68503d631aad","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"include/exec/exec-all: document common exit conditions\n\nAs a precursor to later patches attempt to come up with a more\nconcrete wording for what each of the common exit cases would be.\n\nCC: Emilio G. Cota <cota@braap.org>\nCC: Richard Henderson <rth@twiddle.net>\nCC: Lluís Vilanova <vilanova@ac.upc.edu>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-2-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/df0311e634828fdc99ca59352aef68503d631aad"},{"sha":"e8d5230221851e8933811f1579fd13371f576955","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target/arm/translate: make DISAS_UPDATE match declared semantics\n\nDISAS_UPDATE should be used when the wider CPU state other than just\nthe PC has been updated and we should therefore exit the TCG runtime\nand return to the main execution loop rather assuming DISAS_JUMP would\ndo that.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-3-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/e8d5230221851e8933811f1579fd13371f576955"},{"sha":"abd1fb0ee2c58b99f4b2d15718f1825fe4984e12","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target/arm/translate.h: expand comment on DISAS_EXIT\n\nWe already have an exit condition, DISAS_UPDATE which will exit the\nrun-loop. Expand on the difference with DISAS_EXIT in the comments.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-4-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/abd1fb0ee2c58b99f4b2d15718f1825fe4984e12"},{"sha":"4cae8f56fbab2798586576a56cc669f0127d04fb","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target/arm/translate: ensure gen_goto_tb sets exit flags\n\nAs the gen_goto_tb function can do both static and dynamic jumps it\nshould also set the is_jmp field. This matches the behaviour of the\na64 code.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-5-alex.bennee@linaro.org\n[tweak to multiline comment formatting]\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/4cae8f56fbab2798586576a56cc669f0127d04fb"},{"sha":"0b609cc128ba5ef16cc841bcade898d1898f1dc3","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target/arm: use gen_goto_tb for ISB handling\n\nWhile an ISB will ensure any raised IRQs happen on the next\ninstruction it doesn't cause any to get raised by itself. We can\ntherefore use a simple tb exit for ISB instructions and rely on the\nexit_request check at the top of each TB to deal with exiting if\nneeded.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-6-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/0b609cc128ba5ef16cc841bcade898d1898f1dc3"},{"sha":"b29fd33db578decacd14f34933b29aece3e7c25e","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target/arm: use DISAS_EXIT for eret handling\n\nPreviously DISAS_JUMP did ensure this but with the optimisation of\n8a6b28c7 (optimize indirect branches) we might not leave the loop.\nThis means if any pending interrupts are cleared by changing IRQ flags\nwe might never get around to servicing them. You usually notice this\nby seeing the lookup_tb_ptr() helper gainfully chaining TBs together\nwhile cpu->interrupt_request remains high and the exit_request has not\nbeen set.\n\nThis breaks amongst other things the OPTEE test suite which executes\nan eret from the secure world after a non-secure world IRQ has gone\npending which then never gets serviced.\n\nInstead of using the previously implied semantics of DISAS_JUMP we use\nDISAS_EXIT which will always exit the run-loop.\n\nCC: Etienne Carriere <etienne.carriere@linaro.org>\nCC: Joakim Bech <joakim.bech@linaro.org>\nCC: Jaroslaw Pelczar <j.pelczar@samsung.com>\nCC: Peter Maydell <peter.maydell@linaro.org>\nCC: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-id: 20170713141928.25419-7-alex.bennee@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/b29fd33db578decacd14f34933b29aece3e7c25e"},{"sha":"2eb5578b4794d387e03cd424faa1f0e15c245ab9","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models\n\nModel the ARM MPS2/MPS2+ FPGA based development board.\n\nThe MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger\nFPGA but is otherwise the same as the 2). Since the CPU itself\nand most of the devices are in the FPGA, the details of the board\nas seen by the guest depend significantly on the FPGA image.\n\nWe model the following FPGA images:\n \"mps2_an385\" -- Cortex-M3 as documented in ARM Application Note AN385\n \"mps2_an511\" -- Cortex-M3 'DesignStart' as documented in AN511\n\nThey are fairly similar but differ in the details for some\nperipherals.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1500029487-14822-2-git-send-email-peter.maydell@linaro.org\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/2eb5578b4794d387e03cd424faa1f0e15c245ab9"},{"sha":"775df84e48bffba8cb188eecdf7872923d6e15d7","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART\n\nImplement a model of the simple \"APB UART\" provided in\nthe Cortex-M System Design Kit (CMSDK).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1500029487-14822-3-git-send-email-peter.maydell@linaro.org\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/775df84e48bffba8cb188eecdf7872923d6e15d7"},{"sha":"977a15f4805b0fcc72243581fd9a4e4b6ac4d3b4","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/arm/mps2: Add UARTs\n\nAdd the UARTs to the MPS2 board models.\n\nUnfortunately the details of the wiring of the interrupts through\nvarious OR gates differ between AN511 and AN385 so this can't\nbe purely a data-driven difference.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Alistair Francis <alistair.francis@xilinx.com>\nMessage-id: 1500029487-14822-4-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/977a15f4805b0fcc72243581fd9a4e4b6ac4d3b4"},{"sha":"5dd85b4b48653993335ca20d6e4d7b80129cca97","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device\n\nImplement a model of the simple timer device found in the CMSDK.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nMessage-id: 1500029487-14822-5-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/5dd85b4b48653993335ca20d6e4d7b80129cca97"},{"sha":"3d53904a68ff0532a056e799d7bea6c625ade9ce","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/arm/mps2: Add timers\n\nAdd the CMSDK APB timers to the MPS2 board.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nMessage-id: 1500029487-14822-6-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/3d53904a68ff0532a056e799d7bea6c625ade9ce"},{"sha":"dd73185b7d3f36e9cbb160d739aa1151e55382d0","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller\n\nImplement a model of the Serial Communication Controller (SCC) found\nin MPS2 FPGA images.\n\nThe primary purpose of this device is to communicate with the\nMotherboard Configuration Controller (MCC) which is located on\nthe MPS board itself, outside the FPGA image. This is used\nfor programming the MPS clock generators. The SCC also has\nsome basic ID registers and an output for the board LEDs.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nMessage-id: 1500029487-14822-7-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/dd73185b7d3f36e9cbb160d739aa1151e55382d0"},{"sha":"6dbdf4ec3332dd976ce2b45a431909dedc31bcae","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/arm/mps2: Add SCC\n\nAdd the SCC to the MPS2 board models.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nMessage-id: 1500029487-14822-8-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/6dbdf4ec3332dd976ce2b45a431909dedc31bcae"},{"sha":"3587393922dec51ebcbe6088649aface38cd89f6","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"hw/arm/mps2: Add ethernet\n\nThe MPS2 FPGA images support ethernet via a LAN9220. We use\nQEMU's LAN9118 model, which is software compatible except\nthat it is missing the checksum-offload feature.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1500029487-14822-9-git-send-email-peter.maydell@linaro.org\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/3587393922dec51ebcbe6088649aface38cd89f6"},{"sha":"e5a6a6e64e82a132cebef023d867085b0a2993d7","author":{"name":"Peter Maydell","email":"d4da0cae8bdd6af8ce5950fc7fec7c012df68229@linaro.org"},"message":"MAINTAINERS: Add entries for MPS2 board\n\nAdd entries to the MAINTAINERS file for the new MPS2\nboard and devices.\n\nSince the CMSDK devices are not specific to the MPS2 board,\nextend the existing 'PrimeCell' section to cover CMSDK\ndevices as well; in both cases these are devices implemented\nby ARM and provided as RTL that may be used in multiple\nSoCs and boards.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1500029487-14822-10-git-send-email-peter.maydell@linaro.org\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/e5a6a6e64e82a132cebef023d867085b0a2993d7"},{"sha":"c6c2c0fc32362ba234ae3bdad1a55c2d6aefaa12","author":{"name":"Pavel Dovgalyuk","email":"63adb380a43032adcf7ed73a2f8b968fdd5cb5fc@ispras.ru"},"message":"mips: set CP0 Debug DExcCode for SDBBP instruction\n\nThis patch fixes setting DExcCode field of CP0 Debug register\nwhen SDBBP instruction is executed. According to EJTAG specification,\nthis field must be set to the value 9 (Bp).\n\nSigned-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>\nMessage-id: 20170502120350.3368.92338.stgit@PASHA-ISP\nReviewed-by: Aurelien Jarno <aurelien@aurel32.net>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/c6c2c0fc32362ba234ae3bdad1a55c2d6aefaa12"},{"sha":"06a57e5cc7ee5292a4915117ebf951e310a28264","author":{"name":"Aurelien Jarno","email":"cd2cad3dc514db80899a4324dff884235ca6b264@aurel32.net"},"message":"target/mips: optimize WSBH, DSBH and DSHD\n\nUse the same mask to avoid having to load two different constants.\n\nSuggested-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nSigned-off-by: Aurelien Jarno <aurelien@aurel32.net>","distinct":true,"url":"https://api.github.com/repos/android/platform_external_qemu/commits/06a57e5cc7ee5292a4915117ebf951e310a28264"}]}
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