{"action":"created","comment":{"url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/comments/101254888","pull_request_review_id":21975470,"id":101254888,"diff_hunk":"@@ -5746,245 +5749,1835 @@ gen9_avc_kernel_init(VADriverContextP ctx,\n     generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;\n }\n \n-Bool\n-gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)\n+/*\n+PAK pipeline related function\n+*/\n+extern int\n+intel_avc_enc_slice_type_fixup(int slice_type);\n+\n+static void\n+gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,\n+                              struct encode_state *encode_state,\n+                              struct intel_encoder_context *encoder_context)\n {\n-    /* VME & PAK share the same context */\n-    struct i965_driver_data *i965 = i965_driver_data(ctx);\n-    struct encoder_vme_mfc_context * vme_context = NULL;\n-    struct generic_encoder_context * generic_ctx = NULL;\n-    struct gen9_avc_encoder_context * avc_ctx = NULL;\n-    struct generic_enc_codec_state * generic_state = NULL;\n-    struct avc_enc_state * avc_state = NULL;\n-    struct encoder_status_buffer_internal *status_buffer;\n-    uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;\n+    struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n \n-    vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));\n-    generic_ctx = calloc(1, sizeof(struct generic_encoder_context));\n-    avc_ctx = calloc(1, sizeof(struct gen9_avc_encoder_context));\n-    generic_state = calloc(1, sizeof(struct generic_enc_codec_state));\n-    avc_state = calloc(1, sizeof(struct avc_enc_state));\n+    BEGIN_BCS_BATCH(batch, 5);\n+\n+    OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));\n+    OUT_BCS_BATCH(batch,\n+                  (0 << 29) |\n+                  (MFX_LONG_MODE << 17) |       /* Must be long format for encoder */\n+                  (MFD_MODE_VLD << 15) |\n+                  (0 << 13) |                   /* VDEnc mode  is 1*/\n+                  ((generic_state->curr_pak_pass != (generic_state->num_pak_passes -1)) << 10) |                   /* Stream-Out Enable */\n+                  ((!!avc_ctx->res_post_deblocking_output.bo) << 9)  |    /* Post Deblocking Output */\n+                  ((!!avc_ctx->res_pre_deblocking_output.bo) << 8)  |     /* Pre Deblocking Output */\n+                  (0 << 7)  |                   /* Scaled surface enable */\n+                  (0 << 6)  |                   /* Frame statistics stream out enable, always '1' in VDEnc mode */\n+                  (0 << 5)  |                   /* not in stitch mode */\n+                  (1 << 4)  |                   /* encoding mode */\n+                  (MFX_FORMAT_AVC << 0));\n+    OUT_BCS_BATCH(batch,\n+                  (0 << 7)  | /* expand NOA bus flag */\n+                  (0 << 6)  | /* disable slice-level clock gating */\n+                  (0 << 5)  | /* disable clock gating for NOA */\n+                  (0 << 4)  | /* terminate if AVC motion and POC table error occurs */\n+                  (0 << 3)  | /* terminate if AVC mbdata error occurs */\n+                  (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */\n+                  (0 << 1)  |\n+                  (0 << 0));\n+    OUT_BCS_BATCH(batch, 0);\n+    OUT_BCS_BATCH(batch, 0);\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n \n-    if(!vme_context || !generic_ctx || !avc_ctx || !generic_state || !avc_state)\n-        goto allocate_structure_failed;\n+static void\n+gen9_mfc_avc_surface_state(VADriverContextP ctx,\n+                           struct intel_encoder_context *encoder_context,\n+                           struct i965_gpe_resource *gpe_resource,\n+                           int id)\n+{\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n \n-    memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));\n-    memset(generic_ctx,0,sizeof(struct generic_encoder_context));\n-    memset(avc_ctx,0,sizeof(struct gen9_avc_encoder_context));\n-    memset(generic_state,0,sizeof(struct generic_enc_codec_state));\n-    memset(avc_state,0,sizeof(struct avc_enc_state));\n+    BEGIN_BCS_BATCH(batch, 6);\n+\n+    OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));\n+    OUT_BCS_BATCH(batch, id);\n+    OUT_BCS_BATCH(batch,\n+                  ((gpe_resource->height - 1) << 18) |\n+                  ((gpe_resource->width - 1) << 4));\n+    OUT_BCS_BATCH(batch,\n+                  (MFX_SURFACE_PLANAR_420_8 << 28) |    /* 420 planar YUV surface */\n+                  (1 << 27) |                           /* must be 1 for interleave U/V, hardware requirement */\n+                  ((gpe_resource->pitch - 1) << 3) |    /* pitch */\n+                  (0 << 2)  |                           /* must be 0 for interleave U/V */\n+                  (1 << 1)  |                           /* must be tiled */\n+                  (I965_TILEWALK_YMAJOR << 0));         /* tile walk, TILEWALK_YMAJOR */\n+    OUT_BCS_BATCH(batch,\n+                  (0 << 16) | \t\t\t        /* must be 0 for interleave U/V */\n+                  (gpe_resource->y_cb_offset));         /* y offset for U(cb) */\n+    OUT_BCS_BATCH(batch,\n+                  (0 << 16) | \t\t\t        /* must be 0 for interleave U/V */\n+                  (gpe_resource->y_cb_offset));         /* y offset for U(cb) */\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n \n-    encoder_context->vme_context = vme_context;\n-    vme_context->generic_enc_ctx = generic_ctx;\n-    vme_context->private_enc_ctx = avc_ctx;\n-    vme_context->generic_enc_state = generic_state;\n-    vme_context->private_enc_state = avc_state;\n+static void\n+gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)\n+{\n+    struct i965_driver_data *i965 = i965_driver_data(ctx);\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;\n+    struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n+    int i;\n \n-    if (IS_SKL(i965->intel.device_info)) {\n-        generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;\n-        generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);\n-    }\n-    else\n-        goto allocate_structure_failed;\n+    BEGIN_BCS_BATCH(batch, 65);\n \n-    /* initialize misc ? */\n-    avc_ctx->ctx = ctx;\n-    generic_ctx->use_hw_scoreboard = 1;\n-    generic_ctx->use_hw_non_stalling_scoreboard = 1;\n+    OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (65 - 2));\n \n-    /* initialize generic state */\n+    /* the DW1-3 is for pre_deblocking */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_pre_deblocking_output.bo, 1, 0, 0);\n \n-    generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;\n-    generic_state->preset = INTEL_PRESET_RT_SPEED;\n-    generic_state->seq_frame_number = 0;\n-    generic_state->total_frame_number = 0;\n-    generic_state->frame_type = 0;\n-    generic_state->first_frame = 1;\n+    /* the DW4-6 is for the post_deblocking */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_post_deblocking_output.bo, 1, 0, 0);\n \n-    generic_state->frame_width_in_pixel = 0;\n-    generic_state->frame_height_in_pixel = 0;\n-    generic_state->frame_width_in_mbs = 0;\n-    generic_state->frame_height_in_mbs = 0;\n-    generic_state->frame_width_4x = 0;\n-    generic_state->frame_height_4x = 0;\n-    generic_state->frame_width_16x = 0;\n-    generic_state->frame_height_16x = 0;\n-    generic_state->frame_width_32x = 0;\n-    generic_state->downscaled_width_4x_in_mb = 0;\n-    generic_state->downscaled_height_4x_in_mb = 0;\n-    generic_state->downscaled_width_16x_in_mb = 0;\n-    generic_state->downscaled_height_16x_in_mb = 0;\n-    generic_state->downscaled_width_32x_in_mb = 0;\n-    generic_state->downscaled_height_32x_in_mb = 0;\n+    /* the DW7-9 is for the uncompressed_picture */\n+    OUT_BUFFER_3DW(batch, generic_ctx->res_uncompressed_input_surface.bo, 1, 0, 0);\n \n-    generic_state->hme_supported = 1;\n-    generic_state->b16xme_supported = 1;\n-    generic_state->b32xme_supported = 0;\n-    generic_state->hme_enabled = 0;\n-    generic_state->b16xme_enabled = 0;\n-    generic_state->b32xme_enabled = 0;\n-    generic_state->brc_distortion_buffer_supported = 1;\n-    generic_state->brc_constant_buffer_supported = 0;\n+    /* the DW10-12 is for PAK information (write) */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);//?\n \n+    /* the DW13-15 is for the intra_row_store_scratch */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_intra_row_store_scratch_buffer.bo, 1, 0, 0);\n \n-    generic_state->frame_rate = 30;\n-    generic_state->brc_allocated = 0;\n-    generic_state->brc_inited = 0;\n-    generic_state->brc_need_reset = 0;\n-    generic_state->is_low_delay = 0;\n-    generic_state->brc_enabled = 0;//default\n-    generic_state->internal_rate_mode = 0;\n-    generic_state->curr_pak_pass = 0;\n-    generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;\n-    generic_state->is_first_pass = 1;\n-    generic_state->is_last_pass = 0;\n-    generic_state->mb_brc_enabled = 0; // enable mb brc\n-    generic_state->brc_roi_enable = 0;\n-    generic_state->brc_dirty_roi_enable = 0;\n-    generic_state->skip_frame_enbale = 0;\n+    /* the DW16-18 is for the deblocking filter */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, 0);\n \n-    generic_state->target_bit_rate = 0;\n-    generic_state->max_bit_rate = 0;\n-    generic_state->min_bit_rate = 0;\n-    generic_state->init_vbv_buffer_fullness_in_bit = 0;\n-    generic_state->vbv_buffer_size_in_bit = 0;\n-    generic_state->frames_per_100s = 0;\n-    generic_state->gop_size = 0;\n-    generic_state->gop_ref_distance = 0;\n-    generic_state->brc_target_size = 0;\n-    generic_state->brc_mode = 0;\n-    generic_state->brc_init_current_target_buf_full_in_bits = 0.0;\n-    generic_state->brc_init_reset_input_bits_per_frame = 0.0;\n-    generic_state->brc_init_reset_buf_size_in_bits = 0;\n-    generic_state->brc_init_previous_target_buf_full_in_bits = 0;\n-    generic_state->window_size = 0;//default\n-    generic_state->target_percentage = 0;\n+    /* the DW 19-50 is for Reference pictures*/\n+    for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {\n+        OUT_BUFFER_2DW(batch, avc_ctx->list_reference_res[i].bo, 1, 0);\n+    }\n \n-    generic_state->avbr_curracy = 0;\n-    generic_state->avbr_convergence = 0;\n+    /* DW 51, reference picture attributes */\n+    OUT_BCS_BATCH(batch, 0);\n \n-    generic_state->num_skip_frames = 0;\n-    generic_state->size_skip_frames = 0;\n+    /* The DW 52-54 is for PAK information (read) */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);\n \n-    generic_state->num_roi = 0;\n-    generic_state->max_delta_qp = 0;\n-    generic_state->min_delta_qp = 0;\n+    /* the DW 55-57 is the ILDB buffer */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n \n-    if (encoder_context->rate_control_mode != VA_RC_NONE &&\n-        encoder_context->rate_control_mode != VA_RC_CQP) {\n-        generic_state->brc_enabled = 1;\n-        generic_state->brc_distortion_buffer_supported = 1;\n-        generic_state->brc_constant_buffer_supported = 1;\n-        generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;\n-    }\n-    /*avc state initialization */\n-    avc_state->mad_enable = 0;\n-    avc_state->mb_disable_skip_map_enable = 0;\n-    avc_state->sfd_enable = 1;//default\n-    avc_state->sfd_mb_enable = 1;//set it true\n-    avc_state->adaptive_search_window_enable = 1;//default\n-    avc_state->mb_qp_data_enable = 0;\n-    avc_state->intra_refresh_i_enable = 0;\n-    avc_state->min_max_qp_enable = 0;\n-    avc_state->skip_bias_adjustment_enable = 0;//default,same as   skip_bias_adjustment_supporte? no\n+    /* the DW 58-60 is the second ILDB buffer */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n \n-    //external input\n-    avc_state->non_ftq_skip_threshold_lut_input_enable = 0;\n-    avc_state->ftq_skip_threshold_lut_input_enable = 0;\n-    avc_state->ftq_override = 0;\n+    /* DW 61, memory compress enable & mode */\n+    OUT_BCS_BATCH(batch, 0);\n \n-    avc_state->direct_bias_adjustment_enable = 0;\n-    avc_state->global_motion_bias_adjustment_enable = 0;\n-    avc_state->disable_sub_mb_partion = 0;\n-    avc_state->arbitrary_num_mbs_in_slice = 0;\n-    avc_state->adaptive_transform_decision_enable = 0;//default\n-    avc_state->skip_check_disable = 0;\n-    avc_state->tq_enable = 0;\n-    avc_state->enable_avc_ildb = 0;\n-    avc_state->mbaff_flag = 0;\n-    avc_state->enable_force_skip = 1;//default\n-    avc_state->rc_panic_enable = 1;//default\n-    avc_state->suppress_recon_enable = 1;//default\n+    /* the DW 62-64 is the buffer */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n \n-    avc_state->ref_pic_select_list_supported = 1;\n-    avc_state->mb_brc_supported = 1;//?,default\n-    avc_state->multi_pre_enable = 1;//default\n-    avc_state->ftq_enable = 1;//default\n-    avc_state->caf_supported = 1; //default\n-    avc_state->caf_enable = 0;\n-    avc_state->caf_disable_hd = 1;//default\n-    avc_state->skip_bias_adjustment_supported = 1;//default\n+    ADVANCE_BCS_BATCH(batch);\n+}\n \n-    avc_state->adaptive_intra_scaling_enable = 1;//default\n-    avc_state->old_mode_cost_enable = 0;//default\n-    avc_state->multi_ref_qp_enable = 1;//default\n-    avc_state->weighted_ref_l0_enable = 1;//default\n-    avc_state->weighted_ref_l1_enable = 1;//default\n-    avc_state->weighted_prediction_supported = 0;\n-    avc_state->brc_split_enable = 0;\n-    avc_state->slice_level_report_supported = 0;\n+static void\n+gen9_mfc_avc_ind_obj_base_addr_state(VADriverContextP ctx,\n+                                     struct encode_state *encode_state,\n+                                     struct intel_encoder_context *encoder_context)\n+{\n+    struct i965_driver_data *i965 = i965_driver_data(ctx);\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;\n+    struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n+    struct object_surface *obj_surface;\n+    struct gen9_surface_avc *avc_priv_surface;\n+    unsigned int size = 0;\n+    unsigned int w_mb = generic_state->frame_width_in_mbs;\n+    unsigned int h_mb = generic_state->frame_height_in_mbs;\n \n-    avc_state->fbr_bypass_enable = 1;//default\n-    avc_state->field_scaling_output_interleaved = 0;\n-    avc_state->mb_variance_output_enable = 0;\n-    avc_state->mb_pixel_average_output_enable = 0;\n-    avc_state->rolling_intra_refresh_enable = 0;// same as intra_refresh_i_enable?\n-    avc_state->mbenc_curbe_set_in_brc_update = 0;\n-    avc_state->rounding_inter_enable = 1; //default\n-    avc_state->adaptive_rounding_inter_enable = 1;//default\n+    obj_surface = encode_state->reconstructed_object;\n \n-    avc_state->mbenc_i_frame_dist_in_use = 0;\n-    avc_state->mb_status_supported = 1; //set in intialization for gen9\n-    avc_state->mb_status_enable = 0;\n-    avc_state->mb_vproc_stats_enable = 0;\n-    avc_state->flatness_check_enable = 0;\n-    avc_state->flatness_check_supported = 1;//default\n-    avc_state->block_based_skip_enable = 0;\n-    avc_state->use_widi_mbenc_kernel = 0;\n-    avc_state->kernel_trellis_enable = 0;\n-    avc_state->generic_reserved = 0;\n+    if (!obj_surface || !obj_surface->private_data)\n+        return;\n+    avc_priv_surface = obj_surface->private_data;\n \n-    avc_state->rounding_value = 0;\n-    avc_state->rounding_inter_p = 255;//default\n-    avc_state->rounding_inter_b = 255; //default\n-    avc_state->rounding_inter_b_ref = 255; //default\n-    avc_state->min_qp_i = INTEL_AVC_MIN_QP;\n-    avc_state->min_qp_p = INTEL_AVC_MIN_QP;\n-    avc_state->min_qp_b = INTEL_AVC_MIN_QP;\n-    avc_state->max_qp_i = INTEL_AVC_MAX_QP;\n-    avc_state->max_qp_p = INTEL_AVC_MAX_QP;\n-    avc_state->max_qp_b = INTEL_AVC_MAX_QP;\n+    BEGIN_BCS_BATCH(batch, 26);\n \n-    memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));\n-    memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));\n-    memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));\n+    OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));\n+    /* The DW1-5 is for the MFX indirect bistream offset, ignore for VDEnc mode */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n+    OUT_BUFFER_2DW(batch, NULL, 0, 0);\n \n-    avc_state->intra_refresh_qp_threshold = 0;\n-    avc_state->trellis_flag = 0;\n-    avc_state->hme_mv_cost_scaling_factor = 0;\n-    avc_state->slice_height = 1;\n-    avc_state->slice_num = 1;\n-    memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));\n-    avc_state->bi_weight = 0;\n-    avc_state->brc_const_data_surface_width = 64;\n-    avc_state->brc_const_data_surface_height = 44;\n+    /* the DW6-10 is for MFX Indirect MV Object Base Address, ignore for VDEnc mode */\n+    size = w_mb * h_mb * 32 * 4;\n+    OUT_BUFFER_3DW(batch,\n+                   avc_priv_surface->res_mv_data_surface.bo,\n+                   1,\n+                   0,\n+                   0);\n+    OUT_BUFFER_2DW(batch,\n+                   avc_priv_surface->res_mv_data_surface.bo,\n+                   1,\n+                   ALIGN(size,0x1000));\n+\n+    /* The DW11-15 is for MFX IT-COFF. Not used on encoder */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n+    OUT_BUFFER_2DW(batch, NULL, 0, 0);\n+\n+    /* The DW16-20 is for MFX indirect DBLK. Not used on encoder */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n+    OUT_BUFFER_2DW(batch, NULL, 0, 0);\n+\n+    /* The DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder\n+     * Note: an offset is specified in MFX_AVC_SLICE_STATE\n+     */\n+    OUT_BUFFER_3DW(batch,\n+                   generic_ctx->compressed_bitstream.res.bo,\n+                   1,\n+                   0,\n+                   0);\n+    OUT_BUFFER_2DW(batch,\n+                   generic_ctx->compressed_bitstream.res.bo,\n+                   1,\n+                   generic_ctx->compressed_bitstream.end_offset);\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n \n-    avc_state->num_refs[0] = 0;\n-    avc_state->num_refs[1] = 0;\n-    memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));\n-    memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));\n-    avc_state->tq_rounding = 0;\n-    avc_state->zero_mv_threshold = 0;\n-    avc_state->slice_second_levle_batch_buffer_in_use = 0;\n+static void\n+gen9_mfc_avc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)\n+{\n+    struct i965_driver_data *i965 = i965_driver_data(ctx);\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n \n-    //1. seq/pic/slice\n+    BEGIN_BCS_BATCH(batch, 10);\n \n-    /* the definition of status buffer offset for Encoder */\n+    OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));\n \n-    status_buffer = &avc_ctx->status_buffer;\n-    memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));\n+    /* The DW1-3 is for bsd/mpc row store scratch buffer */\n+    OUT_BUFFER_3DW(batch, avc_ctx->res_bsd_mpc_row_store_scratch_buffer.bo, 1, 0, 0);\n \n-    status_buffer->base_offset = base_offset;\n+    /* The DW4-6 is for MPR Row Store Scratch Buffer Base Address, ignore for encoder */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n+\n+    /* The DW7-9 is for Bitplane Read Buffer Base Address, ignore for encoder */\n+    OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n+\n+static void\n+gen9_mfc_avc_directmode_state(VADriverContextP ctx,\n+                              struct intel_encoder_context *encoder_context)\n+{\n+    struct i965_driver_data *i965 = i965_driver_data(ctx);\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;\n+    struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;\n+\n+    int i;\n+\n+    BEGIN_BCS_BATCH(batch, 71);\n+\n+    OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));\n+\n+    /* Reference frames and Current frames */\n+    /* the DW1-32 is for the direct MV for reference */\n+    for(i = 0; i < NUM_MFC_AVC_DMV_BUFFERS - 2; i += 2) {\n+        if ( avc_ctx->res_direct_mv_buffersr[i].bo != NULL) {\n+            OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[i].bo,\n+                          I915_GEM_DOMAIN_INSTRUCTION, 0,\n+                          0);\n+        } else {\n+            OUT_BCS_BATCH(batch, 0);\n+            OUT_BCS_BATCH(batch, 0);\n+        }\n+    }\n+\n+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);\n+\n+    /* the DW34-36 is the MV for the current reference */\n+    OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS - 2].bo,\n+                  I915_GEM_DOMAIN_INSTRUCTION, 0,\n+                  0);\n+\n+    OUT_BCS_BATCH(batch, i965->intel.mocs_state);\n+\n+    /* POL list */\n+    for(i = 0; i < 32; i++) {\n+        OUT_BCS_BATCH(batch, avc_state->top_field_poc[i]);\n+    }\n+    OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 2]);\n+    OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 1]);\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n+\n+static void\n+gen9_mfc_qm_state(VADriverContextP ctx,\n+                  int qm_type,\n+                  const unsigned int *qm,\n+                  int qm_length,\n+                  struct intel_encoder_context *encoder_context)\n+{\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n+    unsigned int qm_buffer[16];\n+\n+    assert(qm_length <= 16);\n+    assert(sizeof(*qm) == 4);\n+    memset(qm_buffer,0,16*4);\n+    memcpy(qm_buffer, qm, qm_length * 4);\n+\n+    BEGIN_BCS_BATCH(batch, 18);\n+    OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));\n+    OUT_BCS_BATCH(batch, qm_type << 0);\n+    intel_batchbuffer_data(batch, qm_buffer, 16 * 4);\n+    ADVANCE_BCS_BATCH(batch);\n+}\n+\n+static void\n+gen9_mfc_avc_qm_state(VADriverContextP ctx,\n+                      struct encode_state *encode_state,\n+                      struct intel_encoder_context *encoder_context)\n+{\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;\n+    VAEncSequenceParameterBufferH264  *seq_param = avc_state->seq_param;\n+    VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;\n+\n+    /* TODO: add support for non flat matrix */\n+    const unsigned int *qm_4x4_intra;\n+    const unsigned int *qm_4x4_inter;\n+    const unsigned int *qm_8x8_intra;\n+    const unsigned int *qm_8x8_inter;\n+\n+    if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag\n+        && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {\n+        qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;\n+    } else {\n+        VAIQMatrixBufferH264 *qm;\n+        assert(encode_state->q_matrix && encode_state->q_matrix->buffer);\n+        qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;\n+        qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];\n+        qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];\n+        qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];\n+        qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];\n+    }\n+\n+    gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);\n+    gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);\n+    gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);\n+    gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);\n+}\n+\n+static void\n+gen9_mfc_fqm_state(VADriverContextP ctx,\n+                   int fqm_type,\n+                   const unsigned int *fqm,\n+                   int fqm_length,\n+                   struct intel_encoder_context *encoder_context)\n+{\n+    struct intel_batchbuffer *batch = encoder_context->base.batch;\n+    unsigned int fqm_buffer[32];\n+\n+    assert(fqm_length <= 32);\n+    assert(sizeof(*fqm) == 4);\n+    memset(fqm_buffer,0,32*4);\n+    memcpy(fqm_buffer, fqm, fqm_length * 4);\n+\n+    BEGIN_BCS_BATCH(batch, 34);\n+    OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));\n+    OUT_BCS_BATCH(batch, fqm_type << 0);\n+    intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);\n+    ADVANCE_BCS_BATCH(batch);\n+}\n+\n+static void\n+gen9_mfc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)\n+{\n+    int i, j;\n+    for (i = 0; i < len; i++)\n+       for (j = 0; j < len; j++)\n+       {\n+           assert(qm[j * len + i]);\n+           fqm[i * len + j] = (1 << 16) / qm[j * len + i];\n+       }\n+}\n+\n+static void\n+gen9_mfc_avc_fqm_state(VADriverContextP ctx,\n+                      struct encode_state *encode_state,\n+                      struct intel_encoder_context *encoder_context)\n+{\n+    /* TODO: add support for non flat matrix */\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;\n+    VAEncSequenceParameterBufferH264  *seq_param = avc_state->seq_param;\n+    VAEncPictureParameterBufferH264  *pic_param = avc_state->pic_param;\n+\n+    if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag\n+        && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);\n+    } else {\n+        int i;\n+        uint32_t fqm[32];\n+        VAIQMatrixBufferH264 *qm;\n+        assert(encode_state->q_matrix && encode_state->q_matrix->buffer);\n+        qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;\n+\n+        for (i = 0; i < 3; i++)\n+            gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);\n+\n+        for (i = 3; i < 6; i++)\n+            gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);\n+\n+        gen9_mfc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);\n+\n+        gen9_mfc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);\n+        gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);\n+    }\n+}\n+\n+static void\n+gen9_mfc_avc_insert_object(VADriverContextP ctx,\n+                           struct intel_encoder_context *encoder_context,\n+                           unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,\n+                           int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,\n+                           int slice_header_indicator,\n+                           struct intel_batchbuffer *batch)\n+{\n+    if (data_bits_in_last_dw == 0)\n+\tdata_bits_in_last_dw = 32;\n+\n+    BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);\n+\n+    OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws));\n+    OUT_BCS_BATCH(batch,\n+                  (0 << 16) |   /* always start at offset 0 */\n+                  (slice_header_indicator << 14) |\n+                  (data_bits_in_last_dw << 8) |\n+                  (skip_emul_byte_count << 4) |\n+                  (!!emulation_flag << 3) |\n+                  ((!!is_last_header) << 2) |\n+                  ((!!is_end_of_slice) << 1) |\n+                  (0 << 0));    /* TODO: check this flag */\n+    intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);\n+\n+    ADVANCE_BCS_BATCH(batch);\n+}\n+\n+static void\n+gen9_mfc_avc_insert_slice_packed_data(VADriverContextP ctx,\n+                                      struct encode_state *encode_state,\n+                                      struct intel_encoder_context *encoder_context,\n+                                      int slice_index,\n+                                      struct intel_batchbuffer *batch)\n+{\n+    VAEncPackedHeaderParameterBuffer *param = NULL;\n+    unsigned int length_in_bits;\n+    unsigned int *header_data = NULL;\n+    int count, i, start_index;\n+    int slice_header_index;\n+\n+    if (encode_state->slice_header_index[slice_index] == 0)\n+        slice_header_index = -1;\n+    else\n+        slice_header_index = (encode_state->slice_header_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);\n+\n+    count = encode_state->slice_rawdata_count[slice_index];\n+    start_index = (encode_state->slice_rawdata_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);\n+\n+    for (i = 0; i < count; i++) {\n+        unsigned int skip_emul_byte_cnt;\n+\n+        header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;\n+\n+        param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[start_index + i]->buffer);\n+\n+        /* skip the slice header packed data type as it is lastly inserted */\n+        if (param->type == VAEncPackedHeaderSlice)\n+            continue;\n+\n+        length_in_bits = param->bit_length;\n+\n+        skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);\n+\n+        /* as the slice header is still required, the last header flag is set to\n+         * zero.\n+         */\n+        gen9_mfc_avc_insert_object(ctx,\n+                                   encoder_context,\n+                                   header_data,\n+                                   ALIGN(length_in_bits, 32) >> 5,\n+                                   length_in_bits & 0x1f,\n+                                   skip_emul_byte_cnt,\n+                                   0,\n+                                   0,\n+                                   !param->has_emulation_bytes,\n+                                   0,\n+                                   batch);\n+    }\n+\n+    if (slice_header_index == -1) {\n+        VAEncSequenceParameterBufferH264 *seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;\n+        VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;\n+        VAEncSliceParameterBufferH264 *slice_params = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;\n+        unsigned char *slice_header = NULL;\n+        int slice_header_length_in_bits = 0;\n+\n+        /* No slice header data is passed. And the driver needs to generate it */\n+        /* For the Normal H264 */\n+        slice_header_length_in_bits = build_avc_slice_header(seq_param,\n+                                                             pic_param,\n+                                                             slice_params,\n+                                                             &slice_header);\n+        gen9_mfc_avc_insert_object(ctx,\n+                                   encoder_context,\n+                                   (unsigned int *)slice_header,\n+                                   ALIGN(slice_header_length_in_bits, 32) >> 5,\n+                                   slice_header_length_in_bits & 0x1f,\n+                                   5,  /* first 5 bytes are start code + nal unit type */\n+                                   1, 0, 1,\n+                                   1,\n+                                   batch);\n+\n+        free(slice_header);\n+    } else {\n+        unsigned int skip_emul_byte_cnt;\n+\n+        header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;\n+\n+        param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[slice_header_index]->buffer);\n+        length_in_bits = param->bit_length;\n+\n+        /* as the slice header is the last header data for one slice,\n+         * the last header flag is set to one.\n+         */\n+        skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);\n+\n+        gen9_mfc_avc_insert_object(ctx,\n+                                   encoder_context,\n+                                   header_data,\n+                                   ALIGN(length_in_bits, 32) >> 5,\n+                                   length_in_bits & 0x1f,\n+                                   skip_emul_byte_cnt,\n+                                   1,\n+                                   0,\n+                                   !param->has_emulation_bytes,\n+                                   1,\n+                                   batch);\n+    }\n+\n+    return;\n+}\n+\n+static void\n+gen9_mfc_avc_inset_headers(VADriverContextP ctx,\n+                           struct encode_state *encode_state,\n+                           struct intel_encoder_context *encoder_context,\n+                           VAEncSliceParameterBufferH264 *slice_param,\n+                           int slice_index,\n+                           struct intel_batchbuffer *batch)\n+{\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;\n+    int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);\n+    unsigned int internal_rate_mode = generic_state->internal_rate_mode;\n+    unsigned int skip_emul_byte_cnt;\n+\n+    if (slice_index == 0) {\n+        if (encode_state->packed_header_data[idx]) {\n+            VAEncPackedHeaderParameterBuffer *param = NULL;\n+            unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;\n+            unsigned int length_in_bits;\n+\n+            assert(encode_state->packed_header_param[idx]);\n+            param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;\n+            length_in_bits = param->bit_length;\n+\n+            skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);\n+            gen9_mfc_avc_insert_object(ctx,\n+                                       encoder_context,\n+                                       header_data,\n+                                       ALIGN(length_in_bits, 32) >> 5,\n+                                       length_in_bits & 0x1f,\n+                                       skip_emul_byte_cnt,\n+                                       0,\n+                                       0,\n+                                       !param->has_emulation_bytes,\n+                                       0,\n+                                       batch);\n+        }\n+\n+        idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);\n+\n+        if (encode_state->packed_header_data[idx]) {\n+            VAEncPackedHeaderParameterBuffer *param = NULL;\n+            unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;\n+            unsigned int length_in_bits;\n+\n+            assert(encode_state->packed_header_param[idx]);\n+            param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;\n+            length_in_bits = param->bit_length;\n+\n+            skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);\n+\n+            gen9_mfc_avc_insert_object(ctx,\n+                                       encoder_context,\n+                                       header_data,\n+                                       ALIGN(length_in_bits, 32) >> 5,\n+                                       length_in_bits & 0x1f,\n+                                       skip_emul_byte_cnt,\n+                                       0,\n+                                       0,\n+                                       !param->has_emulation_bytes,\n+                                       0,\n+                                       batch);\n+        }\n+\n+        idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);\n+\n+        if (encode_state->packed_header_data[idx]) {\n+            VAEncPackedHeaderParameterBuffer *param = NULL;\n+            unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;\n+            unsigned int length_in_bits;\n+\n+            assert(encode_state->packed_header_param[idx]);\n+            param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;\n+            length_in_bits = param->bit_length;\n+\n+            skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);\n+            gen9_mfc_avc_insert_object(ctx,\n+                                       encoder_context,\n+                                       header_data,\n+                                       ALIGN(length_in_bits, 32) >> 5,\n+                                       length_in_bits & 0x1f,\n+                                       skip_emul_byte_cnt,\n+                                       0,\n+                                       0,\n+                                       !param->has_emulation_bytes,\n+                                       0,\n+                                       batch);\n+        } else if (internal_rate_mode == VA_RC_CBR) {\n+            /* TODO: insert others */\n+        }\n+    }\n+\n+    gen9_mfc_avc_insert_slice_packed_data(ctx,\n+                                          encode_state,\n+                                          encoder_context,\n+                                          slice_index,\n+                                          batch);\n+}\n+\n+static void\n+gen9_mfc_avc_slice_state(VADriverContextP ctx,\n+                         struct encode_state *encode_state,\n+                         struct intel_encoder_context *encoder_context,\n+                         VAEncPictureParameterBufferH264 *pic_param,\n+                         VAEncSliceParameterBufferH264 *slice_param,\n+                         VAEncSliceParameterBufferH264 *next_slice_param,\n+                         struct intel_batchbuffer *batch)\n+{\n+    struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;\n+    struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;\n+    struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;\n+    struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;\n+    unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;\n+    unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;\n+    unsigned char correct[6], grow, shrink;\n+    int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;\n+    int max_qp_n, max_qp_p;\n+    int i;\n+    int weighted_pred_idc = 0;\n+    int num_ref_l0 = 0, num_ref_l1 = 0;\n+    int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);\n+    int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;\n+    unsigned int rc_panic_enable = 0;\n+    unsigned int rate_control_counter_enable = 0;\n+    unsigned int rounding_value = 0;\n+    unsigned int rounding_inter_enable = 0;\n+\n+    //check the inter rounding\n+    if(generic_state->frame_type == SLICE_TYPE_P)\n+    {\n+        if(avc_state->rounding_inter_p == AVC_INVALID_ROUNDING_VALUE)\n+        {\n+            if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))\n+            {\n+                if(generic_state->gop_ref_distance == 1)\n+                    avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p_without_b[slice_qp];\n+                else\n+                    avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p[slice_qp];\n+            }\n+            else\n+            {\n+                avc_state->rounding_value = gen9_avc_inter_rounding_p[generic_state->preset];\n+            }\n+\n+        }else\n+        {\n+            avc_state->rounding_value = avc_state->rounding_inter_p;\n+        }\n+    }else if(generic_state->frame_type == SLICE_TYPE_B)\n+    {\n+        if(pic_param->pic_fields.bits.reference_pic_flag)\n+        {\n+            if(avc_state->rounding_inter_b_ref == AVC_INVALID_ROUNDING_VALUE)\n+                avc_state->rounding_value = gen9_avc_inter_rounding_b_ref[generic_state->preset];\n+            else\n+                avc_state->rounding_value = avc_state->rounding_inter_b_ref;\n+        }\n+        else\n+        {\n+            if(avc_state->rounding_inter_b == AVC_INVALID_ROUNDING_VALUE)\n+            {\n+                if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))\n+                    avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_b[slice_qp];\n+                else\n+                    avc_state->rounding_value = gen9_avc_inter_rounding_b[generic_state->preset];\n+            }else\n+            {\n+                avc_state->rounding_value = avc_state->rounding_inter_b;\n+            }\n+        }\n+    }\n+\n+    slice_hor_pos = slice_param->macroblock_address % generic_state->frame_width_in_mbs;\n+    slice_ver_pos = slice_param->macroblock_address / generic_state->frame_height_in_mbs;\n+\n+    if (next_slice_param) {\n+        next_slice_hor_pos = next_slice_param->macroblock_address % generic_state->frame_width_in_mbs;\n+        next_slice_ver_pos = next_slice_param->macroblock_address / generic_state->frame_height_in_mbs;","path":"src/gen9_avc_encoder.c","position":null,"original_position":986,"commit_id":"d2788c44dd58f8df6e4062772fdf957610f3c861","original_commit_id":"2632d1531e4197b28c14d41be63b412fb22966cd","user":{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false},"body":"it is already fixed in this series of patches. ","created_at":"2017-02-15T11:17:53Z","updated_at":"2017-02-15T11:17:53Z","html_url":"https://github.com/01org/intel-vaapi-driver/pull/33#discussion_r101254888","pull_request_url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33","_links":{"self":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/comments/101254888"},"html":{"href":"https://github.com/01org/intel-vaapi-driver/pull/33#discussion_r101254888"},"pull_request":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33"}}},"pull_request":{"url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33","id":104972927,"html_url":"https://github.com/01org/intel-vaapi-driver/pull/33","diff_url":"https://github.com/01org/intel-vaapi-driver/pull/33.diff","patch_url":"https://github.com/01org/intel-vaapi-driver/pull/33.patch","issue_url":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/33","number":33,"state":"open","locked":false,"title":"AVC Encoder Architecture rework","user":{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false},"body":"Encoder Architecture Changes (Primarily AVC)\r\n\r\nEncoder architecture restructuring for H.264 (with some impact to HEVC now) on HSW+\r\n* Improvements to the shaders\r\n* Improvements to the B frame efficiency\r\n* Improvements to the low bit rate mode\r\n* Improved features in two stage VME/PAK pipeline\r\n\r\nv1:\r\nReduce the patch number and re org for VME and MFX related patches.\r\nPatch re org for VME pipeline\r\nPatch re org for MFX pipeline\r\nkeep assert for internal logic and replace assert for input validation function.\r\nRemove unnecessary comments and enum value.\r\nUse the 64bit version OUT_BCS_RELOC64.\r\nMove kernel binary into header file.\r\nuse misc parameter from encoder_context structure.\r\n\r\nv2:\r\nadd APL support\r\nFor each patch, new file is added in the Makefile.am\r\nFix zero divide issue under cqp\r\nCorrect the license header for the new file.\r\nFix the Batch buffer logic when conditional end enabled.\r\nRemove the execution bit for the files.\r\nmisc changes.\r\n\r\nv3:\r\nrebase to lastest master branch and use i965->intel->media_mocs to configure the memory MOCS.\r\nremove unused enum value \r\n\r\nv4:\r\nuse i965->intel->media_mocs to configure the memory MOCS in PAK pipeline\r\n\r\nReviewed-by: Sean V Kelley<seanvk@posteo.de>\r\nReviewed-by: yakuizhao <yakui.zhao@intel.com>","created_at":"2017-02-07T10:12:55Z","updated_at":"2017-02-15T11:17:53Z","closed_at":null,"merged_at":null,"merge_commit_sha":"36b2ee1f02c5d6c0a1c5f0153a115fd80e51890c","assignee":{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false},"assignees":[{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false}],"milestone":null,"commits_url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33/commits","review_comments_url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33/comments","review_comment_url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/comments{/number}","comments_url":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/33/comments","statuses_url":"https://api.github.com/repos/01org/intel-vaapi-driver/statuses/d2788c44dd58f8df6e4062772fdf957610f3c861","head":{"label":"QuPengfei:avc-enc-improvement-01","ref":"avc-enc-improvement-01","sha":"d2788c44dd58f8df6e4062772fdf957610f3c861","user":{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false},"repo":{"id":81156376,"name":"intel-vaapi-driver","full_name":"QuPengfei/intel-vaapi-driver","owner":{"login":"QuPengfei","id":14069513,"avatar_url":"https://avatars.githubusercontent.com/u/14069513?v=3","gravatar_id":"","url":"https://api.github.com/users/QuPengfei","html_url":"https://github.com/QuPengfei","followers_url":"https://api.github.com/users/QuPengfei/followers","following_url":"https://api.github.com/users/QuPengfei/following{/other_user}","gists_url":"https://api.github.com/users/QuPengfei/gists{/gist_id}","starred_url":"https://api.github.com/users/QuPengfei/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/QuPengfei/subscriptions","organizations_url":"https://api.github.com/users/QuPengfei/orgs","repos_url":"https://api.github.com/users/QuPengfei/repos","events_url":"https://api.github.com/users/QuPengfei/events{/privacy}","received_events_url":"https://api.github.com/users/QuPengfei/received_events","type":"User","site_admin":false},"private":false,"html_url":"https://github.com/QuPengfei/intel-vaapi-driver","description":"VA-API user mode driver for Intel GEN Graphics family","fork":true,"url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver","forks_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/forks","keys_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/keys{/key_id}","collaborators_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/collaborators{/collaborator}","teams_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/teams","hooks_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/hooks","issue_events_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/issues/events{/number}","events_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/events","assignees_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/assignees{/user}","branches_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/branches{/branch}","tags_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/tags","blobs_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/git/blobs{/sha}","git_tags_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/git/tags{/sha}","git_refs_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/git/refs{/sha}","trees_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/git/trees{/sha}","statuses_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/statuses/{sha}","languages_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/languages","stargazers_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/stargazers","contributors_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/contributors","subscribers_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/subscribers","subscription_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/subscription","commits_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/commits{/sha}","git_commits_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/git/commits{/sha}","comments_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/comments{/number}","issue_comment_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/issues/comments{/number}","contents_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/contents/{+path}","compare_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/compare/{base}...{head}","merges_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/merges","archive_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/{archive_format}{/ref}","downloads_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/downloads","issues_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/issues{/number}","pulls_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/pulls{/number}","milestones_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/milestones{/number}","notifications_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/notifications{?since,all,participating}","labels_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/labels{/name}","releases_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/releases{/id}","deployments_url":"https://api.github.com/repos/QuPengfei/intel-vaapi-driver/deployments","created_at":"2017-02-07T02:22:39Z","updated_at":"2017-02-07T02:22:47Z","pushed_at":"2017-02-14T09:53:09Z","git_url":"git://github.com/QuPengfei/intel-vaapi-driver.git","ssh_url":"git@github.com:QuPengfei/intel-vaapi-driver.git","clone_url":"https://github.com/QuPengfei/intel-vaapi-driver.git","svn_url":"https://github.com/QuPengfei/intel-vaapi-driver","homepage":"https://01.org/linuxmedia","size":4116,"stargazers_count":0,"watchers_count":0,"language":"C","has_issues":false,"has_downloads":true,"has_wiki":true,"has_pages":false,"forks_count":0,"mirror_url":null,"open_issues_count":0,"forks":0,"open_issues":0,"watchers":0,"default_branch":"master"}},"base":{"label":"01org:master","ref":"master","sha":"71f77c6a4b757576edb22642cb9baf1cc9792453","user":{"login":"01org","id":1635439,"avatar_url":"https://avatars.githubusercontent.com/u/1635439?v=3","gravatar_id":"","url":"https://api.github.com/users/01org","html_url":"https://github.com/01org","followers_url":"https://api.github.com/users/01org/followers","following_url":"https://api.github.com/users/01org/following{/other_user}","gists_url":"https://api.github.com/users/01org/gists{/gist_id}","starred_url":"https://api.github.com/users/01org/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/01org/subscriptions","organizations_url":"https://api.github.com/users/01org/orgs","repos_url":"https://api.github.com/users/01org/repos","events_url":"https://api.github.com/users/01org/events{/privacy}","received_events_url":"https://api.github.com/users/01org/received_events","type":"Organization","site_admin":false},"repo":{"id":16745248,"name":"intel-vaapi-driver","full_name":"01org/intel-vaapi-driver","owner":{"login":"01org","id":1635439,"avatar_url":"https://avatars.githubusercontent.com/u/1635439?v=3","gravatar_id":"","url":"https://api.github.com/users/01org","html_url":"https://github.com/01org","followers_url":"https://api.github.com/users/01org/followers","following_url":"https://api.github.com/users/01org/following{/other_user}","gists_url":"https://api.github.com/users/01org/gists{/gist_id}","starred_url":"https://api.github.com/users/01org/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/01org/subscriptions","organizations_url":"https://api.github.com/users/01org/orgs","repos_url":"https://api.github.com/users/01org/repos","events_url":"https://api.github.com/users/01org/events{/privacy}","received_events_url":"https://api.github.com/users/01org/received_events","type":"Organization","site_admin":false},"private":false,"html_url":"https://github.com/01org/intel-vaapi-driver","description":"VA-API user mode driver for Intel GEN Graphics family","fork":false,"url":"https://api.github.com/repos/01org/intel-vaapi-driver","forks_url":"https://api.github.com/repos/01org/intel-vaapi-driver/forks","keys_url":"https://api.github.com/repos/01org/intel-vaapi-driver/keys{/key_id}","collaborators_url":"https://api.github.com/repos/01org/intel-vaapi-driver/collaborators{/collaborator}","teams_url":"https://api.github.com/repos/01org/intel-vaapi-driver/teams","hooks_url":"https://api.github.com/repos/01org/intel-vaapi-driver/hooks","issue_events_url":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/events{/number}","events_url":"https://api.github.com/repos/01org/intel-vaapi-driver/events","assignees_url":"https://api.github.com/repos/01org/intel-vaapi-driver/assignees{/user}","branches_url":"https://api.github.com/repos/01org/intel-vaapi-driver/branches{/branch}","tags_url":"https://api.github.com/repos/01org/intel-vaapi-driver/tags","blobs_url":"https://api.github.com/repos/01org/intel-vaapi-driver/git/blobs{/sha}","git_tags_url":"https://api.github.com/repos/01org/intel-vaapi-driver/git/tags{/sha}","git_refs_url":"https://api.github.com/repos/01org/intel-vaapi-driver/git/refs{/sha}","trees_url":"https://api.github.com/repos/01org/intel-vaapi-driver/git/trees{/sha}","statuses_url":"https://api.github.com/repos/01org/intel-vaapi-driver/statuses/{sha}","languages_url":"https://api.github.com/repos/01org/intel-vaapi-driver/languages","stargazers_url":"https://api.github.com/repos/01org/intel-vaapi-driver/stargazers","contributors_url":"https://api.github.com/repos/01org/intel-vaapi-driver/contributors","subscribers_url":"https://api.github.com/repos/01org/intel-vaapi-driver/subscribers","subscription_url":"https://api.github.com/repos/01org/intel-vaapi-driver/subscription","commits_url":"https://api.github.com/repos/01org/intel-vaapi-driver/commits{/sha}","git_commits_url":"https://api.github.com/repos/01org/intel-vaapi-driver/git/commits{/sha}","comments_url":"https://api.github.com/repos/01org/intel-vaapi-driver/comments{/number}","issue_comment_url":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/comments{/number}","contents_url":"https://api.github.com/repos/01org/intel-vaapi-driver/contents/{+path}","compare_url":"https://api.github.com/repos/01org/intel-vaapi-driver/compare/{base}...{head}","merges_url":"https://api.github.com/repos/01org/intel-vaapi-driver/merges","archive_url":"https://api.github.com/repos/01org/intel-vaapi-driver/{archive_format}{/ref}","downloads_url":"https://api.github.com/repos/01org/intel-vaapi-driver/downloads","issues_url":"https://api.github.com/repos/01org/intel-vaapi-driver/issues{/number}","pulls_url":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls{/number}","milestones_url":"https://api.github.com/repos/01org/intel-vaapi-driver/milestones{/number}","notifications_url":"https://api.github.com/repos/01org/intel-vaapi-driver/notifications{?since,all,participating}","labels_url":"https://api.github.com/repos/01org/intel-vaapi-driver/labels{/name}","releases_url":"https://api.github.com/repos/01org/intel-vaapi-driver/releases{/id}","deployments_url":"https://api.github.com/repos/01org/intel-vaapi-driver/deployments","created_at":"2014-02-11T20:58:06Z","updated_at":"2017-02-14T05:22:13Z","pushed_at":"2017-02-15T08:50:35Z","git_url":"git://github.com/01org/intel-vaapi-driver.git","ssh_url":"git@github.com:01org/intel-vaapi-driver.git","clone_url":"https://github.com/01org/intel-vaapi-driver.git","svn_url":"https://github.com/01org/intel-vaapi-driver","homepage":"https://01.org/linuxmedia","size":3978,"stargazers_count":13,"watchers_count":13,"language":"C","has_issues":true,"has_downloads":true,"has_wiki":true,"has_pages":false,"forks_count":11,"mirror_url":null,"open_issues_count":28,"forks":11,"open_issues":28,"watchers":13,"default_branch":"master"}},"_links":{"self":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33"},"html":{"href":"https://github.com/01org/intel-vaapi-driver/pull/33"},"issue":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/33"},"comments":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/issues/33/comments"},"review_comments":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33/comments"},"review_comment":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/comments{/number}"},"commits":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/pulls/33/commits"},"statuses":{"href":"https://api.github.com/repos/01org/intel-vaapi-driver/statuses/d2788c44dd58f8df6e4062772fdf957610f3c861"}}}}
{"actor":{"display_login":"QuPengfei"}}