{"push_id":2108798657,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"ae848f871947825dbdc889bf4b0bb4c0fd92219f","before":"5bcb23ebbb85d9616f8ba2a82e48178559b350e6","commits":[{"sha":"bf9429252264a31d7b3aa87967031aa83b0f529f","author":{"name":"Maximilian Schander","email":"deb47b92a194708f6e1fa7d4d03f1f5201d32468@mimoja.de"},"message":"util/autoport: Fix VGA register warning\n\nThe warning is printed using Printf syntax but actually Println is used\nresulting in printing the format string first and the arguments second:\n\"%s. (%s) Default:%s WARNING: [...]\"\n\nChange-Id: I411fc47832dd7a82752f233c4909b98190340ccb\nSigned-off-by: Maximilian Schander <coreboot@mimoja.de>\nReviewed-on: https://review.coreboot.org/22352\nTested-by: build bot (Jenkins) <no-reply@coreboot.org>\nReviewed-by: Patrick Rudolph <siro@das-labor.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/bf9429252264a31d7b3aa87967031aa83b0f529f"},{"sha":"98c11ddc9e95f15a8c10b212e9bfc1180dc83369","author":{"name":"Maximilian Schander","email":"deb47b92a194708f6e1fa7d4d03f1f5201d32468@mimoja.de"},"message":"util/inteltool: Add Skylake DMIBAR register dumping\n\nRegister definitions were taken from\n * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2\n * Page 117\n * 332688-003EN\nAs well as\n * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2\n * Page 117\n * 332987-002EN\n\nTested on a 6th gen skylake mobile cpu and capability registers do match up\nwith the default values.\n\nChange-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e\nSigned-off-by: Maximilian Schander <coreboot@mimoja.de>\nReviewed-on: https://review.coreboot.org/22345\nTested-by: build bot (Jenkins) <no-reply@coreboot.org>\nReviewed-by: Nico Huber <nico.h@gmx.de>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/98c11ddc9e95f15a8c10b212e9bfc1180dc83369"},{"sha":"798564333d541ab29abe210f818a500a7582baf7","author":{"name":"Maximilian Schander","email":"deb47b92a194708f6e1fa7d4d03f1f5201d32468@mimoja.de"},"message":"util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake\n\nBoth registers behave the same as on the previous generation\n\nTaken from\n * 6th Generation Intel Processor Families for S-Platform\n     Volume 2 of 2\n * Page 55 and 62\n * 332688-003EN\n\nChange-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9\nSigned-off-by: Maximilian Schander <coreboot@mimoja.de>\nReviewed-on: https://review.coreboot.org/22350\nTested-by: build bot (Jenkins) <no-reply@coreboot.org>\nReviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>\nReviewed-by: Nico Huber <nico.h@gmx.de>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/798564333d541ab29abe210f818a500a7582baf7"},{"sha":"ae848f871947825dbdc889bf4b0bb4c0fd92219f","author":{"name":"Maximilian Schander","email":"deb47b92a194708f6e1fa7d4d03f1f5201d32468@mimoja.de"},"message":"util/inteltool: Add Skylake definition to MCHBAR reading\n\nTaken from\n   * 6th Generation Intel Processor Families for S-Platform \n       Volume 2 of 2\n   * Page 56\n   * 332688-003EN\n\nChange-Id: I46c8dd77823870b55cc040f7f6c557cb5a2562a1\nSigned-off-by: Maximilian Schander <coreboot@mimoja.de>\nReviewed-on: https://review.coreboot.org/22351\nTested-by: build bot (Jenkins) <no-reply@coreboot.org>\nReviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>\nReviewed-by: Nico Huber <nico.h@gmx.de>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/ae848f871947825dbdc889bf4b0bb4c0fd92219f"}]}
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