{"push_id":2061665069,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"941790d494f9ac22877d2f3c33b089eb5e08cd7b","before":"3f756ad85f4b22927f6b07a91ecf9757ef7ebcd3","commits":[{"sha":"941790d494f9ac22877d2f3c33b089eb5e08cd7b","author":{"name":"Gustavo Adolfo Garcia","email":"e8d0a6740e765e2a10f16d4fe0c5722e66cf3910@users.noreply.github.com"},"message":"VHDL Module Arithmetic Logic Unit (ALU)\n\nVHDL Module Arithmetic Logic Unit (ALU)","distinct":true,"url":"https://api.github.com/repos/gustavogarciautp/Procesador/commits/941790d494f9ac22877d2f3c33b089eb5e08cd7b"}]}
{"actor":{"display_login":"gustavogarciautp"}}