{"push_id":1560179438,"size":35,"distinct_size":0,"ref":"refs/heads/utilities","head":"e08c3030101e63deb61e29d90624a65477faa929","before":"03addc598e21db429e1bf34baf4ef77282bcb4cb","commits":[{"sha":"520e07716d17b4ec2b1920972093aa11104ad717","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: Add --show and --hide parameters\n\nAdd the \"--show\" and \"--hide\" cmdline parameters.\n\nBy default, turbostat shows all columns.\n\nturbostat --hide counter_list\nwill continue showing all columns, except for those listed.\n\nturbostat --show counter_list\nwill show _only_ the listed columns\n\nThese features work for built-in counters, and have no effect\non columns added with the --add parameter.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/520e07716d17b4ec2b1920972093aa11104ad717"},{"sha":"10344fcc785bc935d5349717fc3330ec36ca933a","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT\n\nand so --debug fails with:\n\nturbostat: msr 1 offset 0x1aa read failed: Input/output error\n\nIt seems that baytrail, and airmont do not have this MSR.\nIt is included in subsequent Goldmont Atom.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/10344fcc785bc935d5349717fc3330ec36ca933a"},{"sha":"11b83bcfa19ae024c803bb43e616f38952f36833","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration\n\nwith --debug, see:\n\ncpu0: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-CC6-Demotion)\ncpu0: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-MC6-Demotion)\n\nNote that the hardware default is to enable demotion,\nand Linux started clearing these registers in 3.17.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/11b83bcfa19ae024c803bb43e616f38952f36833"},{"sha":"9421ed64873e92e5e994d3b52a26712806ba3c0b","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: Baytrail: remove debug line in quiet mode\n\nWithout --debug, a debug line was printed on Baytrail:\n\nSLM BCLK: 83.3 Mhz\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/9421ed64873e92e5e994d3b52a26712806ba3c0b"},{"sha":"d08e6c7b3c5673a83e647528041e148aadbb8f52","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: update MSR_PKG_CST_CONFIG_CONTROL decoding\n\nAMT value 0 is unlimited, not PC0\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/d08e6c7b3c5673a83e647528041e148aadbb8f52"},{"sha":"559633a94da8a29dca1929f0b0f148578e81da47","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"x86: define MSR_PKG_CST_CONFIG_CONTROL\n\ndefine MSR_PKG_CST_CONFIG_CONTROL (0xE2),\nwhich is the string used by Intel Documentation.\n\nWe use this MSR in intel_idle and turbostat by a previous name,\nto be updated in the next patch.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/559633a94da8a29dca1929f0b0f148578e81da47"},{"sha":"d0f10a73ca61286109b02593da270ad8318ef3ce","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"intel_idle: use new name for MSR_PKG_CST_CONFIG_CONTROL\n\npreviously known as  MSR_NHM_SNB_PKG_CST_CFG_CTL\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/d0f10a73ca61286109b02593da270ad8318ef3ce"},{"sha":"c3019af3cede8ea53a85e694120555147c3824d3","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: use new name for MSR_PKG_CST_CONFIG_CONTROL\n\nPreviously called MSR_NHM_SNB_PKG_CST_CFG_CTL\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/c3019af3cede8ea53a85e694120555147c3824d3"},{"sha":"c8c44e2ce8317fd32b1ed935fb7557ebc9e8bdf5","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"x86: msr-index.h: remove unused MSR_NHM_SNB_PKG_CST_CFG_CTL\n\nThe two users, intel_idle driver and turbostat utility\nare using the new name, MSR_PKG_CST_CONFIG_CONTROL\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/c8c44e2ce8317fd32b1ed935fb7557ebc9e8bdf5"},{"sha":"adf47af11e9c0da8d6800a009eb0728f1b1886fa","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: Baytrail c-state support\n\nThe Baytrail SOC, with its Silvermont core, has some unique properties:\n\n1. a hardware CC1 residency counter\n2. a module-c6 residency counter\n3. a package-c6 counter at traditional package-c7 counter address.\n\nThe SOC does not support c3, pc3, c7 or pc7 counters.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/adf47af11e9c0da8d6800a009eb0728f1b1886fa"},{"sha":"b322e7f061d9a8f8c24f181950021fd7e2281c30","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: add precision to --debug frequency output\n\nAdd a digit of precision to the --debug output for frequency range.\nThis is useful when BCLK is not an integer.\n\nold:\n6 * 83 = 500 MHz max efficiency frequency\n26 * 83 = 2166 MHz base frequency\n\nnew:\n6 * 83.3 = 499.8 MHz max efficiency frequency\n26 * 83.3 = 2165.8 MHz base frequency\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/b322e7f061d9a8f8c24f181950021fd7e2281c30"},{"sha":"d4475c22b6669f082b31d8d63629d6a4f0a6b708","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: further decode MSR_IA32_MISC_ENABLE\n\nDecode MISC_ENABLE.NO_TURBO,\nalso use the #defines in msr-index.h for decoding this register\n\ncpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)\n\nAlthough it is not architectural, decode also\nMSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).\ndocumented to be present on: Core, P4, Intel-Xeon\nreserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/d4475c22b6669f082b31d8d63629d6a4f0a6b708"},{"sha":"5b10754d6770eea7672602bf7125bc9f6b0d8efd","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"x86 msr-index.h: Define Atom specific core ratio MSR locations\n\nThese MSRs are currently used by the intel_pstate driver,\nusing a local definition.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/5b10754d6770eea7672602bf7125bc9f6b0d8efd"},{"sha":"d9ae6a36ba6ad66e50ee1c4348847c52cd327b55","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"intel_pstate: use MSR_ATOM_RATIOS definitions from msr-index.h\n\nOriginally, these MSRs were locally defined in this driver.\nNow the definitions are in msr-index.h -- use them.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/d9ae6a36ba6ad66e50ee1c4348847c52cd327b55"},{"sha":"b1c9a89cc626102c46a05bce297efc1daf3da8f2","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: dump Atom P-states correctly\n\nTurbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture.\nBut Atom Architecture uses MSR_ATOM_CORE_RATIOS and\nMSR_ATOM_CORE_TURBO_RATIOS.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/b1c9a89cc626102c46a05bce297efc1daf3da8f2"},{"sha":"786adab2f7a1b823a4056b808faf7328f34e14e5","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: decode CPUID(6).TURBO\n\nshow the CPUID feature for turbo to clarify the case\nwhen it may not be shown in MISC_ENABLE\n\nCPUID(6): APERF, TURBO, DTS, PTM, No-HWP, No-HWPnotify, No-HWPwindow, No-HWPepp, No-HWPpkg, EPB\ncpu4: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/786adab2f7a1b823a4056b808faf7328f34e14e5"},{"sha":"57a8de8a3c3498f7251f689ff586b6548e1be85b","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"x86 msr_index.h: define MSR_MISC_FEATURE_CONTROL\n\nThis non-architectural MSR has disable bits\nfor various prefetchers on modern processors.\n\nWhile these bits are generally touched only by the BIOS,\nsay, via BIOS SETUP, it is useful to dump them\nwhen examining options that can alter performance.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/57a8de8a3c3498f7251f689ff586b6548e1be85b"},{"sha":"568d6272fc207a0622d7064995acf8302bc1d62c","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL\n\nuseful for observing if the BIOS disabled prefetch\nNot architectural, but docuemented as present on NHM, SNB\nand is present on others.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/568d6272fc207a0622d7064995acf8302bc1d62c"},{"sha":"3854dfcbe5db2794a51919666ffe1c9856de6127","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: show all columns, independent of --debug\n\nSome time ago, turbostat overflowed 80 columns.\n\nSo on the assumption that a \"casual\" user would always\nwant topology and frequency columns, we hid the rest\nof the columns and the system configuration decoding\nbehind the --debug option.\n\nNot everybody liked that change -- including me.\nI use --debug 99% of the time...\n\nWell, now we have \"-o file\" to put turbostat output into a file,\nso unless you are watching real-time in a small window,\ncolumn count is less frequently a factor.\n\nAnd more recently, we got the \"--hide columnA,columnB\" option\nto specify columns to skip.\n\nSo now we \"un-hide\" the rest of the columns from behind --debug,\nand show them all, by default.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/3854dfcbe5db2794a51919666ffe1c9856de6127"},{"sha":"59e6338bc3de3900a8d0b8b6db0eddb9328cabc4","author":{"name":"Len Brown","email":"5d565dd5e9539f4ecdf383fcf3bb78b1a67861cb@intel.com"},"message":"tools/power turbostat: print system config, unless --quiet\n\nSome users want turbostat to tell them everything, by default.\nSome users want turbostat to be quiet, by default.\n\nI find that I'm in the 1st camp, and so I've never liked\nneeding to type the --debug parameter to decode the system\nconfiguration.\n\nSo here we change the default and print the system configuration,\nby default.  (The --debug option is now un-documented, though\nit does still exist for debugging turbostat internals)\n\nWhen you do not want to see the system configuration\nheader, use the new \"--quiet\" option.\n\nSigned-off-by: Len Brown <len.brown@intel.com>","distinct":false,"url":"https://api.github.com/repos/lenb/linux/commits/59e6338bc3de3900a8d0b8b6db0eddb9328cabc4"}]}
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