{"push_id":1627409365,"size":5,"distinct_size":5,"ref":"refs/heads/master","head":"f885500f47b2dd12c751a2cd6cab07cbd679d00d","before":"8b2132abbea2f562fcc51468318d55c736f9cad0","commits":[{"sha":"92b0e9b3cb849ab348873242cdb74e8b72b2c74c","author":{"name":"Jonas Paulsson","email":"4c93e2886b64de531beb8b929d8fad48e40017c9@linux.vnet.ibm.com"},"message":"[DAGTypeLegalizer]  Handle widening truncate to vector of i1.\n\nPreviously, PromoteIntRes_TRUNCATE() did not handle the case where\nthe operand needs widening, which resulted in llvm_unreachable().\n\nThis patch adds the needed handling, along with a test case.\n\nReview: Eli Friedman, Simon Pilgrim.\nhttps://reviews.llvm.org/D31077\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298357 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/92b0e9b3cb849ab348873242cdb74e8b72b2c74c"},{"sha":"c2eb9ef056b977a5185059f394d073d2d2afdd2d","author":{"name":"Volkan Keles","email":"dd8ba9e21a622bb892e4efe1073661cdcb2fd7e7@apple.com"},"message":"[GlobalISel] Move isTriviallyDead to Utils. NFC.\n\nMake it accessible by the targets to avoid code duplication.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298358 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/c2eb9ef056b977a5185059f394d073d2d2afdd2d"},{"sha":"1ec8346b667232713d90f199de6e15f434acf486","author":{"name":"Artur Pilipenko","email":"d4943161b8169600bef82d433258916312b12ab5@azulsystems.com"},"message":"NFC. InstCombiner::visitFAdd extract LHSIntVal/RHSIntVal local variables\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298359 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/1ec8346b667232713d90f199de6e15f434acf486"},{"sha":"26b9b438fdda2dbfe8e37005cb33f5dc6b9c5e19","author":{"name":"Andrea Di Biagio","email":"4e5edfb90c567dbfaca12b358bdd86282318fab7@sn.scee.net"},"message":"[DebugInfo][X86] Teach Optimize LEAs pass to handle debug values\n\nThis patch fixes an issue in the Optimize LEAs pass where redundant LEAs were\nnot removed because they were being used by debug values. The debug values are\nnow ignored when determining whether LEAs are redundant.\n\nFor now the debug values for the redundant LEAs are marked as undefined,\neffectively lost. The intention is for a follow up patch which will attempt to\npreserve the debug values where possible.\n\nPatch by Andrew Ng.\n\nDifferential Revision: https://reviews.llvm.org/D30835\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298360 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/26b9b438fdda2dbfe8e37005cb33f5dc6b9c5e19"},{"sha":"f885500f47b2dd12c751a2cd6cab07cbd679d00d","author":{"name":"Sam Kolton","email":"8a6c015f0dc467308554d2ac9d26fdecd6408c1d@amd.com"},"message":"[ADMGPU] SDWA peephole optimization pass.\n\nSummary:\nFirst iteration of SDWA peephole.\n\nThis pass tries to combine several instruction into one SDWA instruction. E.g. it converts:\n'''\n    V_LSHRREV_B32_e32 %vreg0, 16, %vreg1\n    V_ADD_I32_e32 %vreg2, %vreg0, %vreg3\n    V_LSHLREV_B32_e32 %vreg4, 16, %vreg2\n'''\nInto:\n'''\n   V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD\n'''\n\nPass structure:\n    1. Iterate over machine instruction in basic block and try to apply \"SDWA patterns\" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.\n    2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''\n    3. Iterate over all potential instructions and check if they can be converted into SDWA.\n    4. Convert instructions to SDWA.\n\nThis review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).\nThere are several ways this pass can be improved:\n    1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.\n    2. Introduce more SDWA patterns\n    3. Introduce mnemonics to limit when SDWA patterns should apply\n\nReviewers: vpykhtin, alex-t, arsenm, rampitec\n\nSubscribers: wdng, nhaehnle, mgorny\n\nDifferential Revision: https://reviews.llvm.org/D30038\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298365 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/f885500f47b2dd12c751a2cd6cab07cbd679d00d"}]}
{"actor":{"display_login":"kraj"}}