{"action":"opened","issue":{"url":"https://api.github.com/repos/cliffordwolf/picorv32/issues/38","repository_url":"https://api.github.com/repos/cliffordwolf/picorv32","labels_url":"https://api.github.com/repos/cliffordwolf/picorv32/issues/38/labels{/name}","comments_url":"https://api.github.com/repos/cliffordwolf/picorv32/issues/38/comments","events_url":"https://api.github.com/repos/cliffordwolf/picorv32/issues/38/events","html_url":"https://github.com/cliffordwolf/picorv32/issues/38","id":214488358,"number":38,"title":"Xilinx ISE 14.7 synthesis","user":{"login":"pmonta","id":528118,"avatar_url":"https://avatars3.githubusercontent.com/u/528118?v=3","gravatar_id":"","url":"https://api.github.com/users/pmonta","html_url":"https://github.com/pmonta","followers_url":"https://api.github.com/users/pmonta/followers","following_url":"https://api.github.com/users/pmonta/following{/other_user}","gists_url":"https://api.github.com/users/pmonta/gists{/gist_id}","starred_url":"https://api.github.com/users/pmonta/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/pmonta/subscriptions","organizations_url":"https://api.github.com/users/pmonta/orgs","repos_url":"https://api.github.com/users/pmonta/repos","events_url":"https://api.github.com/users/pmonta/events{/privacy}","received_events_url":"https://api.github.com/users/pmonta/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2017-03-15T18:43:04Z","updated_at":"2017-03-15T18:43:04Z","closed_at":null,"body":"A few changes are needed for successful synthesis by the legacy Xilinx ISE toolchain:\r\n\r\n- xst incorrectly implements the register file with ENABLE_REGS_DUALPORT = 1, but ENABLE_REGS_DUALPORT = 0 works fine\r\n- xst doesn't like memory in an always @* combinational block\r\n- xst has some problems with parameterized macros\r\n\r\nI did look at issues #2 and #25, and I'm a little puzzled as to how synthesis even completed, unless they made the same changes to the RTL as I did.  I haven't seen problems with the PC register once the design is in runnable shape.\r\n\r\nAttached is an example project targeting the Spartan 3E Starter board.  It contains a picorv32 core with the plain memory interface, some block RAM, a UART, and some test software in C.\r\n\r\nI'm just putting this out there in the hope it will make picorv32 more useful for older Spartan-6 or Spartan-3E designs; the main repository probably doesn't want to deal with irksome `ifdef OLD_XILINX stuff.  I have some Spartan-6 hardware for which I'd like to use picorv32 (currently using picoblaze).\r\n\r\n[picorv32-Xilinx-ISE.tar.gz](https://github.com/cliffordwolf/picorv32/files/845646/picorv32-Xilinx-ISE.tar.gz)\r\n"}}
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