{"push_id":2166881859,"size":3,"distinct_size":3,"ref":"refs/heads/master","head":"afa43721a57ca5532f35992246960bc16f0a0a66","before":"9d8ec2be86c5db7ce2fc4a0c8c19042f00d8e187","commits":[{"sha":"bcbe76f641409733b4eca5a723e6f01dd14aff11","author":{"name":"Sam Shen","email":"8dff3c0903b890782b8257098927c2fa8f88861b@users.noreply.github.com"},"message":"make sure block size\n\nto make sure the block size must be 16,\nI used a different ID: 371536, and tested this memory has different size. shown on modelsim. read addr 0 then read addr 8 takes 3 cycle. read addr 0 then 16 takes 17 cycles. 0 then 32 takes 17 cycles. 0 then 64 takes 47 cycles. 0 then 128 takes 112 cycles(max). take means this ID have different size. But mine should have same size. since besides 0 and 8. others all gives max hit time 102.","distinct":true,"url":"https://api.github.com/repos/wssrcok/Comp-Arch-lab5/commits/bcbe76f641409733b4eca5a723e6f01dd14aff11"},{"sha":"22f470ae2d955fbf44ababb83bd4d428fe2ef950","author":{"name":"Sam Shen","email":"8dff3c0903b890782b8257098927c2fa8f88861b@users.noreply.github.com"},"message":"L2 # of blocks is 32\n\nfrom line 257 to line 264. the for loop is set up to have each loop runs one block of cache memory. at line 257 for i < 32. the readMem at address 0 on line 265 always take 16 cycles. however, when the 33rd blocks is read. the hit time increased to 42. Which means the L2 cache runs out of blocks and a capacity miss happened. We have to go to L3 to get the Mem[0].","distinct":true,"url":"https://api.github.com/repos/wssrcok/Comp-Arch-lab5/commits/22f470ae2d955fbf44ababb83bd4d428fe2ef950"},{"sha":"afa43721a57ca5532f35992246960bc16f0a0a66","author":{"name":"Sam Shen","email":"8dff3c0903b890782b8257098927c2fa8f88861b@users.noreply.github.com"},"message":"# of Blocks for L3 is 64\n\nuse the same idea for L2 cache. when i < 64 on line 257. It takes 42 cycles. when it is changed to i < 65. It takes 102 cycles to get Mem[0]. It proves L3 cache have 64 blocks.","distinct":true,"url":"https://api.github.com/repos/wssrcok/Comp-Arch-lab5/commits/afa43721a57ca5532f35992246960bc16f0a0a66"}]}
{"actor":{"display_login":"wssrcok"}}