{"action":"created","issue":{"url":"https://api.github.com/repos/dotnet/coreclr/issues/14371","repository_url":"https://api.github.com/repos/dotnet/coreclr","labels_url":"https://api.github.com/repos/dotnet/coreclr/issues/14371/labels{/name}","comments_url":"https://api.github.com/repos/dotnet/coreclr/issues/14371/comments","events_url":"https://api.github.com/repos/dotnet/coreclr/issues/14371/events","html_url":"https://github.com/dotnet/coreclr/issues/14371","id":263593361,"number":14371,"title":"[Arm64] Support for Vector Intrinsics and/or SIMD requires 128bit argument registers to be preserved","user":{"login":"sdmaclea","id":25674984,"avatar_url":"https://avatars3.githubusercontent.com/u/25674984?v=4","gravatar_id":"","url":"https://api.github.com/users/sdmaclea","html_url":"https://github.com/sdmaclea","followers_url":"https://api.github.com/users/sdmaclea/followers","following_url":"https://api.github.com/users/sdmaclea/following{/other_user}","gists_url":"https://api.github.com/users/sdmaclea/gists{/gist_id}","starred_url":"https://api.github.com/users/sdmaclea/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sdmaclea/subscriptions","organizations_url":"https://api.github.com/users/sdmaclea/orgs","repos_url":"https://api.github.com/users/sdmaclea/repos","events_url":"https://api.github.com/users/sdmaclea/events{/privacy}","received_events_url":"https://api.github.com/users/sdmaclea/received_events","type":"User","site_admin":false},"labels":[{"id":310938377,"url":"https://api.github.com/repos/dotnet/coreclr/labels/arch-arm64","name":"arch-arm64","color":"eb6420","default":false}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":5,"created_at":"2017-10-06T22:59:12Z","updated_at":"2017-10-10T00:17:14Z","closed_at":null,"author_association":"MEMBER","body":"@dotnet/jit-contrib @dotnet/arm64-contrib \r\n\r\nThe following logic and assumptions will no longer be true when SIMD intrinsic support is added.\r\n``` C++\r\n//--------------------------------------------------------------------\r\n// This represents the floating point argument registers which are saved\r\n// as part of the NegInfo for a FramedMethodFrame. Note that these\r\n// might not be saved by all stubs: typically only those that call into\r\n// C++ helpers will need to preserve the values in these volatile\r\n// registers.\r\n//--------------------------------------------------------------------\r\ntypedef DPTR(struct FloatArgumentRegisters) PTR_FloatArgumentRegisters;\r\nstruct FloatArgumentRegisters {\r\n    // armV8 supports 32 floating point registers. Each register is 128bits long.\r\n    // It can be accessed as 128-bit value or 64-bit value(d0-d31) or as 32-bit value (s0-s31)\r\n    // or as 16-bit value or as 8-bit values. C# only has two builtin floating datatypes float(32-bit) and \r\n    // double(64-bit). It does not have a quad-precision floating point.So therefore it does not make sense to\r\n    // store full 128-bit values in Frame when the upper 64 bit will not contain any values.\r\n    double  d[8];  // d0-d7\r\n};\r\n```\r\n\r\nI plan to change this to save ful 128-bits all the time.  If there are any objections, let me know.\r\n\r\nThis will also affect `SAVE_FLOAT_ARGUMENT_REGISTERS` and `RESTORE_FLOAT_ARGUMENT_REGISTERS` macros and related assembly frame layouts"},"comment":{"url":"https://api.github.com/repos/dotnet/coreclr/issues/comments/335323423","html_url":"https://github.com/dotnet/coreclr/issues/14371#issuecomment-335323423","issue_url":"https://api.github.com/repos/dotnet/coreclr/issues/14371","id":335323423,"user":{"login":"jkotas","id":6668460,"avatar_url":"https://avatars2.githubusercontent.com/u/6668460?v=4","gravatar_id":"","url":"https://api.github.com/users/jkotas","html_url":"https://github.com/jkotas","followers_url":"https://api.github.com/users/jkotas/followers","following_url":"https://api.github.com/users/jkotas/following{/other_user}","gists_url":"https://api.github.com/users/jkotas/gists{/gist_id}","starred_url":"https://api.github.com/users/jkotas/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jkotas/subscriptions","organizations_url":"https://api.github.com/users/jkotas/orgs","repos_url":"https://api.github.com/users/jkotas/repos","events_url":"https://api.github.com/users/jkotas/events{/privacy}","received_events_url":"https://api.github.com/users/jkotas/received_events","type":"User","site_admin":false},"created_at":"2017-10-10T00:17:14Z","updated_at":"2017-10-10T00:17:14Z","author_association":"MEMBER","body":"The hardware intrinsics are inlined most of the time. In the rare cases where the hardware intrinsics are called as method (e.g. if you call them via reflection), the arguments are passed to them as regular arguments (not HVAs) today."}}
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