{"push_id":1896895444,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"0414d8c2636f73c8effc043fca1c63cbec93d8a8","before":"277dff28b41d44856cffefe5458070f1cad3304c","commits":[{"sha":"0414d8c2636f73c8effc043fca1c63cbec93d8a8","author":{"name":"Daniel Sanders","email":"11d7e2af1a379271955e5fef131dc5a28fc141a8@apple.com"},"message":"[globalisel][tablegen] Do not merge memoperands from instructions that weren't in the match.\n\nSummary:\nFix a bug discovered in an out-of-tree target where memoperands from\npseudo-instructions that weren't part of the match were being merged into the\nresult instructions as part of GIR_MergeMemOperands.\n\nThis bug was caused by a change to the handling of State.MIs between rules when\nthe state machine tables were fused into a single table. Previously, each rule\nwould reset State.MIs using State.MIs.resize(1) but this is no longer done, as a\nresult stale data is occasionally left in some elements of State.MIs. Most\nopcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands\nfrom the intructions recorded in State.MIs into the result instruction.\n\nSuppose for example, we processed but rejected the following pattern:\n  (signextend (load x))\nat this point, State.MIs contains the signextend and the load. Now suppose we\nprocess and accept this pattern:\n  (add x, y)\nat this point, State.MIs contains the add as well as the (now irrelevant) load.\nWhen GIR_MergeMemOperands is processed, the memoperands from that irrelevant\nload will be merged into the result instruction even though it was not part of\nthe match.\n\nBringing back the State.MIs.resize(1) would fix the problem but it would limit\nour ability to optimize the table in the future. Instead, this patch fixes the\nproblem by explicitly stating which instructions should be merged into the result.\n\nThere's no direct test case in this commit because a test case would be very brittle.\nHowever, at the time of writing this should fix the failures in\nhttp://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/ as well as a\nfailure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled.\n\nReviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar\n\nSubscribers: fhahn, kristof.beyls, igorb, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D36094","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-20170507/commits/0414d8c2636f73c8effc043fca1c63cbec93d8a8"}]}
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