{"push_id":1683712489,"size":827,"distinct_size":827,"ref":"refs/heads/master","head":"603e72e193c997a85648463175c80979ffe4c6d1","before":"ab3be33d40cede6c9e610c05d07b057254f57317","commits":[{"sha":"c7506ed12457e5a24b35967d65b138eeb787582b","author":{"name":"Chad Rosier","email":"e952f8aa3e67effe457298fd1b65a8202b705b98@codeaurora.org"},"message":"[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.\n\nAmong other things, this allows Machine LICM to hoist a costly 'mrs'\ninstruction from within a loop.\n\nDifferential Revision: http://reviews.llvm.org/D31151\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298851 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/c7506ed12457e5a24b35967d65b138eeb787582b"},{"sha":"cb5431a93155c5c6a522848d8568712d4cf3baa5","author":{"name":"Dmitry Preobrazhensky","email":"2fff238649643f8ccf6388213f9658c9bab72388@amd.com"},"message":"[AMDGPU][MC] Fix for Bug 28207 + LIT tests\n\nEnabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type\n\nReviewers: vpykhtin, arsenm\n\nDifferential Revision: https://reviews.llvm.org/D31327\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298852 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/cb5431a93155c5c6a522848d8568712d4cf3baa5"},{"sha":"460b732910215b7ec7a3796242647723dc0998a6","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Use proper constant types in test. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298854 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/460b732910215b7ec7a3796242647723dc0998a6"},{"sha":"fb6a2d6627b042255635be7daca52fa2985b94f7","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel] Add a 'getConstantVRegVal' helper.\n\nUse it to compare immediate operands.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298855 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/fb6a2d6627b042255635be7daca52fa2985b94f7"},{"sha":"2597299d8e56be362addf6dc441a404ffa266783","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Select CBZ.\n\nCBZ/CBNZ represent a substantial portion of all conditional branches.\nLook through G_ICMP to select them.\n\nWe can't use tablegen yet because the existing patterns match an\nAArch64ISD node.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298856 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/2597299d8e56be362addf6dc441a404ffa266783"},{"sha":"2a867a816ec71aa28dd168949192b7b40efe9370","author":{"name":"Valery Pykhtin","email":"e634843e76a2d89faff5aeb169c374be10f679ab@amd.com"},"message":"[AMDGPU] Fix SI scheduler LiveOut Refcount issue\n\nPatch by Axel Davy (axel.davy@normalesup.org)\n\nDifferential revision: https://reviews.llvm.org/D30145\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298857 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/2a867a816ec71aa28dd168949192b7b40efe9370"},{"sha":"82ba8a62686b97ebda4578162a632fbdcc36af35","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[APInt] Move the >64 bit case for flipAllBits out of line.\n\nThis is more consistent with what we do for other operations. This shrinks the opt binary on my build by ~72k.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298858 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/82ba8a62686b97ebda4578162a632fbdcc36af35"},{"sha":"96f1d455e70f87127bad58f14186836946bd57b3","author":{"name":"Valery Pykhtin","email":"e634843e76a2d89faff5aeb169c374be10f679ab@amd.com"},"message":"[AMDGPU] SISched: Update colorEndsAccordingToDependencies\n\nPatch by Axel Davy (axel.davy@normalesup.org)\n\nDifferential revision: https://reviews.llvm.org/D30150\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298861 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/96f1d455e70f87127bad58f14186836946bd57b3"},{"sha":"3d5ea4cd1311a3c3c072e211da0249337dfce66d","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Select store of zero to WZR/XZR.\n\nThese occur very frequently, and are quite trivial to catch.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298862 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/3d5ea4cd1311a3c3c072e211da0249337dfce66d"},{"sha":"db6b71ba7954fad8e37a9c53ec84de95c3ae177e","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.\n\nWe're not to the point of supporting the load/store patterns yet\n(because they extensively use PatFrags).\n\nBut in the meantime, we can implement some of the simplest addressing\nmodes.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298863 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/db6b71ba7954fad8e37a9c53ec84de95c3ae177e"},{"sha":"97874bddd63328616c18a0e8230f6732c02ba3ba","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.\n\nA majority of loads and stores at O0 access an alloca.\n\nIt's trivial to fold the G_FRAME_INDEX into the instruction; do it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298864 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/97874bddd63328616c18a0e8230f6732c02ba3ba"},{"sha":"573d120591e9ac339ab0467aebbdeef4cc482cea","author":{"name":"Adrian Prantl","email":"3b76fbf1c74594027f839a53c333f1ac0d409492@apple.com"},"message":"Remove unneccessary virtual destructor from DwarfExpression.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298865 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/573d120591e9ac339ab0467aebbdeef4cc482cea"},{"sha":"91a21c4db6409d2b6c4d0b8e57ec1dfa73451663","author":{"name":"Adrian Prantl","email":"3b76fbf1c74594027f839a53c333f1ac0d409492@apple.com"},"message":"Remove redundant check for nullptr.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298866 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/91a21c4db6409d2b6c4d0b8e57ec1dfa73451663"},{"sha":"31355ac4355e59814af0435f8a3327495a12d229","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[APInt] Use memset in setAllBits.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298867 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/31355ac4355e59814af0435f8a3327495a12d229"},{"sha":"c53cf7e424b8014a647330d8317566bba7699a6d","author":{"name":"Ahmed Bougacha","email":"f94c8c31282d444042829284d0628a0bd66a3a17@gmail.com"},"message":"[GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.\n\nr298863 used PtrReg, but that's never defined in release builds. Fix it.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298869 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/c53cf7e424b8014a647330d8317566bba7699a6d"},{"sha":"0532ee926c28ac0abda1d4181123974ec6bd1507","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[APInt] Move operator&=(uint64_t) inline and use memset to clear the upper words.\n\nThis method is pretty new and probably isn't use much in the code base so this should have a negligible size impact. The OR and XOR operators are already inline.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298870 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/0532ee926c28ac0abda1d4181123974ec6bd1507"},{"sha":"fa92ec8e9e59d57a1556ec7b2024de94001485ae","author":{"name":"Bruno Cardoso Lopes","email":"aa5b4b0fe96f40a92b197547f2a96952081c3ea1@gmail.com"},"message":"[Support] Avoid concurrency hazard in signal handler registration\n\nSeveral static functions from the signal API can be invoked\nsimultaneously; RemoveFileOnSignal for instance can be called indirectly\nby multiple parallel loadModule() invocations, which might lead to\nthe assertion:\n\nAssertion failed: (NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) && \"Out of space for signal handlers!\"),\n  function RegisterHandler, file /llvm/lib/Support/Unix/Signals.inc, line 105.\n\nRemoveFileOnSignal calls RegisterHandlers(), which isn't currently\nmutex protected, leading to the behavior above. This potentially affect\na few other users of RegisterHandlers() too.\n\nrdar://problem/30381224\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298871 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/fa92ec8e9e59d57a1556ec7b2024de94001485ae"},{"sha":"bc04e5d6d238dd5b4564eda726cf64cefe83377f","author":{"name":"Valery Pykhtin","email":"e634843e76a2d89faff5aeb169c374be10f679ab@amd.com"},"message":"[AMDGPU] SISched: Detect dependency types between blocks\n\nPatch by Axel Davy (axel.davy@normalesup.org)\n\nDifferential revision: https://reviews.llvm.org/D30153\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298872 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/bc04e5d6d238dd5b4564eda726cf64cefe83377f"},{"sha":"daa7fe44b1f005091edb5d14706f01e8bf29bfdc","author":{"name":"Krzysztof Parzyszek","email":"40979b2c4eb65586fe7bead22e2c9fb24795e47a@codeaurora.org"},"message":"[TableGen] Print #nnn as a name of an non-native reg unit with id nnn\n\nWhen using -debug with -gen-register-info, tablegen will crash when\ntrying to print a name of a non-native register unit. This patch only\naffects the debug information generated while running llvm-tblgen,\nand has no impact on the compilable code coming out of it.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298875 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/daa7fe44b1f005091edb5d14706f01e8bf29bfdc"},{"sha":"28ec1cc8922def174d48a19134644780c5960584","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[APInt] Move operator=(uint64_t) inline as its pretty simple and is often used with small constants that the compiler can optimize.\n\nWhile there recognize that we only need to clearUnusedBits on the single word case.\n\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298881 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/eliben/llvm/commits/28ec1cc8922def174d48a19134644780c5960584"}]}
{"actor":{"display_login":"eliben"}}