{"push_id":1659398322,"size":34,"distinct_size":34,"ref":"refs/heads/master","head":"336fea27b0d54b7e996398d10010a8fc35e0e136","before":"acb4cc678cf0f145b33bcaa11c241e7c1bc44e1c","commits":[{"sha":"a230fe2a47f681496e5818668197bacbb52cab57","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"[Arm64/Windows] Backport #9500 changes\n\nFixes #9526","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/a230fe2a47f681496e5818668197bacbb52cab57"},{"sha":"15f2e26d4cdc2ad4a2b1ac5b1386c29640602bf8","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"[Arm64/Windows] Revert changes per #10260 & review","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/15f2e26d4cdc2ad4a2b1ac5b1386c29640602bf8"},{"sha":"5d1922d82e7e418769ccf5b173188966d26dbe4d","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"[Arm64/Windows] Fix per review comment","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/5d1922d82e7e418769ccf5b173188966d26dbe4d"},{"sha":"e59ab7b62492173eae2be6f96723c2500e080868","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"Fix unwinding issue caught by CI\n\nDebugged by Rahul Kumar (Thanks)","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/e59ab7b62492173eae2be6f96723c2500e080868"},{"sha":"4db5a72bc2209c6f56c7f335ae318f79d1fe2a4f","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"Use PROLOG_SAVE_REG_PAIR_NO_FP per review comments","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/4db5a72bc2209c6f56c7f335ae318f79d1fe2a4f"},{"sha":"80a314c64b1e850d1ee6e10e9792a13ae90b22bd","author":{"name":"Steve MacLean, Qualcomm Datacenter Technologies, Inc","email":"f5707b07564eac69351f12669f97b5328830be1d@qti.qualcomm.com"},"message":"[Arm64] Fix GCStress hole in genReturn","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/80a314c64b1e850d1ee6e10e9792a13ae90b22bd"},{"sha":"201c70cc49ff2027fb8ed0ba5e25f56534b04a96","author":{"name":"Rahul Kumar","email":"328de7336c502e686bd5152d4ee6dc54f5921228@microsoft.com"},"message":"1. Remove disable of C4996\n2. delete some dead code\n3. Remove implementation of GetOSVersion and hardcode OS version to be 0.0.0\n4. Add implementation of IsWindows8OrAbove & IsWinrtSupported (donno why this was deleted earlier)\n5. remove GetVersionEx from PAL","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/201c70cc49ff2027fb8ed0ba5e25f56534b04a96"},{"sha":"4561dad3f38f8dd5a9637fc3a0be418abac1f088","author":{"name":"noahfalk","email":"6d09e63c1c89e86b36954f4b2a7ecba9079eaabf@microsoft.com"},"message":"Add Tier0/1 jit flags\n\nThese flags provides a hook to change the JIT policy in the future and diverge tier0/tier1 compilation from min_opt/speed_opt respectively.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/4561dad3f38f8dd5a9637fc3a0be418abac1f088"},{"sha":"6f40552c88ac826647b787f6b433e359aacfe574","author":{"name":"Alexander Soldatov","email":"d7f3338052c9411b965f19d63ce2e167d8ce4473@samsung.com"},"message":"[RyuJIT/ARM32] GS Cookie check implementation.\n\nImplementation of GS Cookie check for RyuJIT/ARM32 almost the same as\nfor ARM64. So this code was moved to codegencommon with.\nAlso added optimization to use tmp register for emitting helper call.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/6f40552c88ac826647b787f6b433e359aacfe574"},{"sha":"20917a1ece166167734f3ece02882e3c444da121","author":{"name":"Alexander Soldatov","email":"d7f3338052c9411b965f19d63ce2e167d8ce4473@samsung.com"},"message":"[RyuJIT/ARM32] Localloc implementation in codegen\n\nAlgorithm is almost the same as for other platforms but code\nis little bit refactored to improve readability.\n\nAdded test to cover almost all possible branches of codegen.\nSince arrays allocation of int type is needed multiplication and overflow\nchecks new tests cover only byte arrays.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/20917a1ece166167734f3ece02882e3c444da121"},{"sha":"c7a2eebf97893a3b7cf45e1713225805dddf8e71","author":{"name":"Bruce Forstall","email":"74743cd806e5cc8aa129b22f4e1c9e76e37958d3@microsoft.com"},"message":"Add Linux host support for arm32/arm64 altjit\n\nNow, on Linux, the x64 build will build an arm64-targeting\naltjit. The x86 build will build an arm32-targeting JIT.\nThe altjit is named libprotononjit.so/dylib. It can be\nused for debugging or for generating asm diffs using jit-diff.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/c7a2eebf97893a3b7cf45e1713225805dddf8e71"},{"sha":"b9fd50477279cca8badc453dde294661693a111c","author":{"name":"Bruce Forstall","email":"74743cd806e5cc8aa129b22f4e1c9e76e37958d3@microsoft.com"},"message":"Remove unused code under typo define\n\nThe code is under COR_JIT_EE_VER which never existed (it used to\nbe COR_JIT_EE_VERSION), thus the code has never been used.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/b9fd50477279cca8badc453dde294661693a111c"},{"sha":"9264c062d0c2da0b38544da01a4d23e18df1d62c","author":{"name":"Ben Adams","email":"a5309959088d99f7b2ab41daca566bfdf14b0f71@illyriad.co.uk"},"message":"Improve Guid.ToString (#10669)\n\n* Improve Guid.ToString\r\n\r\n* revert HexToChar","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/9264c062d0c2da0b38544da01a4d23e18df1d62c"},{"sha":"b8f4ad63fbd1c0401c49189fb1c05081d07fe6b3","author":{"name":"Matt Warren","email":"85026721eddec5f5c797eb4a8979d2a087ad1d0e@live.co.uk"},"message":"Move '#pragma warning(disable:21000)' to correct place (#10455)\n\nWhilst I was writing a blog post ['A Hitchhikers Guide to the CoreCLR Source Code'](http://mattwarren.org/2017/03/23/Hitchhikers-Guide-to-the-CoreCLR-Source-Code/#top-10-lists) I noticed that a `#pragma warning(disable:21000)` was mis-aligned.\r\n\r\nI'm pretty sure that having it in the wrong place doesn't cause a problem (i.e. this doesn't actually *fix* anything), because the other methods are smaller, so I understand if you don't want to take the PR.","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/b8f4ad63fbd1c0401c49189fb1c05081d07fe6b3"},{"sha":"2c57c010b96a188c7b01aab318321a5baed18476","author":{"name":"Nicolò Carandini","email":"a1a27d12c5cba85aee540edd3aef301dbde52e04@users.noreply.github.com"},"message":"Update README.md (#10641)\n\nIn this file I’ve found a “project.json” occurrence that I've changed to \".csproj\".","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/2c57c010b96a188c7b01aab318321a5baed18476"},{"sha":"4c1df4be63a79a4375691b1de49e890913733cec","author":{"name":"Noah Falk","email":"6d09e63c1c89e86b36954f4b2a7ecba9079eaabf@users.noreply.github.com"},"message":"Merge pull request #10580 from noahfalk/fitjit_tier0_flag\n\nAdd Tier0 jit flag","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/4c1df4be63a79a4375691b1de49e890913733cec"},{"sha":"f66e306a08b3f8de10d6ad26faccd53b58a56b7e","author":{"name":"Bruce Forstall","email":"74743cd806e5cc8aa129b22f4e1c9e76e37958d3@microsoft.com"},"message":"Merge pull request #10682 from BruceForstall/CleanUpJitEEDefine\n\nRemove unused code under typo define","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/f66e306a08b3f8de10d6ad26faccd53b58a56b7e"},{"sha":"ebf4927d891757b1bd7f54119de2ad60900d3232","author":{"name":"Rahul Kumar","email":"328de7336c502e686bd5152d4ee6dc54f5921228@microsoft.com"},"message":"Merge pull request #10601 from rahku/c4996\n\n1. Remove disable of C4996","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/ebf4927d891757b1bd7f54119de2ad60900d3232"},{"sha":"53c88123a7f6216a31318f14062fd245730c74ba","author":{"name":"Jonghyun Park","email":"8597e43723f6fb7eb642f8222d1eb6622ca38829@gmail.com"},"message":"[x86/Linux] Correctly unwind esp frames (#10685)","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/53c88123a7f6216a31318f14062fd245730c74ba"},{"sha":"dfce3af2ee5967ae53c7b47135f150f59452ded3","author":{"name":"Hyeongseok Oh","email":"2255b956ef3d68220d01c468457d92bdfd6b5984@samsung.com"},"message":"Pass crossbuild and linux-id to CMakeLists.txt using CMake arguments (#10686)\n\nRemove in CMakeLists.txt\r\n1) read cross-build from environment variable\r\n2) read linux-id from file system\r\nInstead, pass cross-build and linux-id from gen-buildsys-clang.sh using cmake arguments","distinct":true,"url":"https://api.github.com/repos/briansull/coreclr/commits/dfce3af2ee5967ae53c7b47135f150f59452ded3"}]}
{"actor":{"display_login":"briansull"}}