{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel3/issues/608","repository_url":"https://api.github.com/repos/ucb-bar/chisel3","labels_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/608/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/608/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/608/events","html_url":"https://github.com/ucb-bar/chisel3/issues/608","id":226434632,"number":608,"title":"SyncReadMem strange read behavior after rdEn gets deasserted","user":{"login":"aayupov","id":16566085,"avatar_url":"https://avatars3.githubusercontent.com/u/16566085?v=3","gravatar_id":"","url":"https://api.github.com/users/aayupov","html_url":"https://github.com/aayupov","followers_url":"https://api.github.com/users/aayupov/followers","following_url":"https://api.github.com/users/aayupov/following{/other_user}","gists_url":"https://api.github.com/users/aayupov/gists{/gist_id}","starred_url":"https://api.github.com/users/aayupov/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/aayupov/subscriptions","organizations_url":"https://api.github.com/users/aayupov/orgs","repos_url":"https://api.github.com/users/aayupov/repos","events_url":"https://api.github.com/users/aayupov/events{/privacy}","received_events_url":"https://api.github.com/users/aayupov/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2017-05-04T23:18:37Z","updated_at":"2017-05-04T23:30:01Z","closed_at":null,"body":"I am seeing that the read data output port gets an X (random) value in FIRRTL interpreter when I deassert rdEn in the previous cycle whereas I would expect the port to keep the previous read data instead. In fact, the generated verilog behaves as I expected. Do you think it is a bug or this is intentional? As far as I know all sequential memories behave as I would like here."},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel3/issues/comments/299336772","html_url":"https://github.com/ucb-bar/chisel3/issues/608#issuecomment-299336772","issue_url":"https://api.github.com/repos/ucb-bar/chisel3/issues/608","id":299336772,"user":{"login":"aswaterman","id":1031106,"avatar_url":"https://avatars3.githubusercontent.com/u/1031106?v=3","gravatar_id":"","url":"https://api.github.com/users/aswaterman","html_url":"https://github.com/aswaterman","followers_url":"https://api.github.com/users/aswaterman/followers","following_url":"https://api.github.com/users/aswaterman/following{/other_user}","gists_url":"https://api.github.com/users/aswaterman/gists{/gist_id}","starred_url":"https://api.github.com/users/aswaterman/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/aswaterman/subscriptions","organizations_url":"https://api.github.com/users/aswaterman/orgs","repos_url":"https://api.github.com/users/aswaterman/repos","events_url":"https://api.github.com/users/aswaterman/events{/privacy}","received_events_url":"https://api.github.com/users/aswaterman/received_events","type":"User","site_admin":false},"created_at":"2017-05-04T23:30:01Z","updated_at":"2017-05-04T23:30:01Z","body":"ASIC SRAMs, which SyncReadMem needs to model, generally have undefined outputs after the read-enable is not asserted."}}
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