{"action":"created","issue":{"url":"https://api.github.com/repos/pulp-platform/pulpino/issues/114","repository_url":"https://api.github.com/repos/pulp-platform/pulpino","labels_url":"https://api.github.com/repos/pulp-platform/pulpino/issues/114/labels{/name}","comments_url":"https://api.github.com/repos/pulp-platform/pulpino/issues/114/comments","events_url":"https://api.github.com/repos/pulp-platform/pulpino/issues/114/events","html_url":"https://github.com/pulp-platform/pulpino/issues/114","id":257660924,"number":114,"title":"Netlist generation and simulation","user":{"login":"FrischAd","id":9270833,"avatar_url":"https://avatars3.githubusercontent.com/u/9270833?v=4","gravatar_id":"","url":"https://api.github.com/users/FrischAd","html_url":"https://github.com/FrischAd","followers_url":"https://api.github.com/users/FrischAd/followers","following_url":"https://api.github.com/users/FrischAd/following{/other_user}","gists_url":"https://api.github.com/users/FrischAd/gists{/gist_id}","starred_url":"https://api.github.com/users/FrischAd/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/FrischAd/subscriptions","organizations_url":"https://api.github.com/users/FrischAd/orgs","repos_url":"https://api.github.com/users/FrischAd/repos","events_url":"https://api.github.com/users/FrischAd/events{/privacy}","received_events_url":"https://api.github.com/users/FrischAd/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":47,"created_at":"2017-09-14T09:55:13Z","updated_at":"2017-11-24T14:57:58Z","closed_at":"2017-09-14T10:30:35Z","author_association":"NONE","body":"Hello,\r\nI generated a netlist using Design Compiler.\r\nI have two issues:\r\n1. In sp_ram_wrap.sv is a module called 'sp_ram_bank' but there is no file containing this module. Where can I find it?\r\n2. I generated the netlist by using the 'sp_ram' and not the 'sp_ram_bank'. Is it possible to simulate this netlist with your provided scripts or alter them easily? If not, how did you verify that the netlist is correct? (Formal verification?)\r\n\r\nThanks in advance."},"comment":{"url":"https://api.github.com/repos/pulp-platform/pulpino/issues/comments/346846299","html_url":"https://github.com/pulp-platform/pulpino/issues/114#issuecomment-346846299","issue_url":"https://api.github.com/repos/pulp-platform/pulpino/issues/114","id":346846299,"user":{"login":"FrancescoConti","id":7882682,"avatar_url":"https://avatars2.githubusercontent.com/u/7882682?v=4","gravatar_id":"","url":"https://api.github.com/users/FrancescoConti","html_url":"https://github.com/FrancescoConti","followers_url":"https://api.github.com/users/FrancescoConti/followers","following_url":"https://api.github.com/users/FrancescoConti/following{/other_user}","gists_url":"https://api.github.com/users/FrancescoConti/gists{/gist_id}","starred_url":"https://api.github.com/users/FrancescoConti/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/FrancescoConti/subscriptions","organizations_url":"https://api.github.com/users/FrancescoConti/orgs","repos_url":"https://api.github.com/users/FrancescoConti/repos","events_url":"https://api.github.com/users/FrancescoConti/events{/privacy}","received_events_url":"https://api.github.com/users/FrancescoConti/received_events","type":"User","site_admin":false},"created_at":"2017-11-24T14:57:58Z","updated_at":"2017-11-24T14:57:58Z","author_association":"OWNER","body":"As stated previously by @FrischAd, you have to provide a clock gating cell that will connect the input `clk_i` to the internal (possibly gated) `clk`.\r\n\r\nSequential power, as defined by Design Compiler, refers to the amount of power spent within sequential blocks (flip-flops, latches) as opposed to that spent inside combinational blocks or in the interconnects. Of course it makes no sense for it to be 0. In general, you shouldn't trust power reports unless they are intuitively reasonable. Moreover, 1) post-synthesis power reports are much more unrealistic (optimistic) than post-layout ones - topological synthesis helps quite a bit 2) power reports obtained without switching activities collected directly with simulations on the netlist are *not reliable* at all and can be wildly incorrect.\r\nI have no idea what you mean by the following assertion:\r\n> External clock (input) only needs to be given for synthesis and power analysis.\r\nIn general, you can say that having something \"broken\" on the clock path will break your synthesis real fast. Registers not reached by a clock will be optimized away (i.e. removed) and power, area and timing results will cease to make any sense. Correctly specifying clocks is one of the keys to correct RTL-to-gates synthesis.\r\n\r\nHonestly from your questions it appears you are lacking some preliminary knowledge necessary to be productive in doing synthesis and power analysis. I can recommend you do some preliminary study on textbooks (e.g. some on [this list](https://www.amazon.com/s/ref=nb_sb_noss?url=search-alias%3Daps&field-keywords=digital+vlsi+design&rh=i%3Aaps%2Ck%3Adigital+vlsi+design) contain decent introductions to using Design Compiler among other tools), ask around on StackOverflow or - if you have this possibility - ask more expert people in your group/department to guide you, which is definitely the best option. The PULPino issue tracker is unfortunately _not the proper place_ to learn how to properly work on synthesis."}}
{"actor":{"display_login":"FrancescoConti"}}