{"action":"created","issue":{"url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/68","repository_url":"https://api.github.com/repos/matthijskooijman/arduino-lmic","labels_url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/68/labels{/name}","comments_url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/68/comments","events_url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/68/events","html_url":"https://github.com/matthijskooijman/arduino-lmic/issues/68","id":208092775,"number":68,"title":"Arduino error for SX1276 module","user":{"login":"ramesh493","id":2602595,"avatar_url":"https://avatars.githubusercontent.com/u/2602595?v=3","gravatar_id":"","url":"https://api.github.com/users/ramesh493","html_url":"https://github.com/ramesh493","followers_url":"https://api.github.com/users/ramesh493/followers","following_url":"https://api.github.com/users/ramesh493/following{/other_user}","gists_url":"https://api.github.com/users/ramesh493/gists{/gist_id}","starred_url":"https://api.github.com/users/ramesh493/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ramesh493/subscriptions","organizations_url":"https://api.github.com/users/ramesh493/orgs","repos_url":"https://api.github.com/users/ramesh493/repos","events_url":"https://api.github.com/users/ramesh493/events{/privacy}","received_events_url":"https://api.github.com/users/ramesh493/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2017-02-16T11:18:07Z","updated_at":"2017-02-17T04:55:28Z","closed_at":null,"body":"Startting Failure\r\n\r\nC:\\Users\\XXX\\Desktop\\Sketch\\libraries\\arduino-lmic-master\\src\\lmic\\radio.c 689\r\n\r\nI have tried with 1.6.10, 1.6.11 and latest version of arduino.\r\n\r\nradio.c code which i am using \r\n\r\n/*******************************************************************************\r\n * Copyright (c) 2014-2015 IBM Corporation.\r\n * All rights reserved. This program and the accompanying materials\r\n * are made available under the terms of the Eclipse Public License v1.0\r\n * which accompanies this distribution, and is available at\r\n * http://www.eclipse.org/legal/epl-v10.html\r\n *\r\n * Contributors:\r\n *    IBM Zurich Research Lab - initial API, implementation and documentation\r\n *******************************************************************************/\r\n\r\n#include \"lmic.h\"\r\n\r\n// ----------------------------------------\r\n// Registers Mapping\r\n#define RegFifo                                    0x00 // common\r\n#define RegOpMode                                  0x01 // common\r\n#define FSKRegBitrateMsb                           0x02\r\n#define FSKRegBitrateLsb                           0x03\r\n#define FSKRegFdevMsb                              0x04\r\n#define FSKRegFdevLsb                              0x05\r\n#define RegFrfMsb                                  0x06 // common\r\n#define RegFrfMid                                  0x07 // common\r\n#define RegFrfLsb                                  0x08 // common\r\n#define RegPaConfig                                0x09 // common\r\n#define RegPaRamp                                  0x0A // common\r\n#define RegOcp                                     0x0B // common\r\n#define RegLna                                     0x0C // common\r\n#define FSKRegRxConfig                             0x0D\r\n#define LORARegFifoAddrPtr                         0x0D\r\n#define FSKRegRssiConfig                           0x0E\r\n#define LORARegFifoTxBaseAddr                      0x0E\r\n#define FSKRegRssiCollision                        0x0F\r\n#define LORARegFifoRxBaseAddr                      0x0F\r\n#define FSKRegRssiThresh                           0x10\r\n#define LORARegFifoRxCurrentAddr                   0x10\r\n#define FSKRegRssiValue                            0x11\r\n#define LORARegIrqFlagsMask                        0x11\r\n#define FSKRegRxBw                                 0x12\r\n#define LORARegIrqFlags                            0x12\r\n#define FSKRegAfcBw                                0x13\r\n#define LORARegRxNbBytes                           0x13\r\n#define FSKRegOokPeak                              0x14\r\n#define LORARegRxHeaderCntValueMsb                 0x14\r\n#define FSKRegOokFix                               0x15\r\n#define LORARegRxHeaderCntValueLsb                 0x15\r\n#define FSKRegOokAvg                               0x16\r\n#define LORARegRxPacketCntValueMsb                 0x16\r\n#define LORARegRxpacketCntValueLsb                 0x17\r\n#define LORARegModemStat                           0x18\r\n#define LORARegPktSnrValue                         0x19\r\n#define FSKRegAfcFei                               0x1A\r\n#define LORARegPktRssiValue                        0x1A\r\n#define FSKRegAfcMsb                               0x1B\r\n#define LORARegRssiValue                           0x1B\r\n#define FSKRegAfcLsb                               0x1C\r\n#define LORARegHopChannel                          0x1C\r\n#define FSKRegFeiMsb                               0x1D\r\n#define LORARegModemConfig1                        0x1D\r\n#define FSKRegFeiLsb                               0x1E\r\n#define LORARegModemConfig2                        0x1E\r\n#define FSKRegPreambleDetect                       0x1F\r\n#define LORARegSymbTimeoutLsb                      0x1F\r\n#define FSKRegRxTimeout1                           0x20\r\n#define LORARegPreambleMsb                         0x20\r\n#define FSKRegRxTimeout2                           0x21\r\n#define LORARegPreambleLsb                         0x21\r\n#define FSKRegRxTimeout3                           0x22\r\n#define LORARegPayloadLength                       0x22\r\n#define FSKRegRxDelay                              0x23\r\n#define LORARegPayloadMaxLength                    0x23\r\n#define FSKRegOsc                                  0x24\r\n#define LORARegHopPeriod                           0x24\r\n#define FSKRegPreambleMsb                          0x25\r\n#define LORARegFifoRxByteAddr                      0x25\r\n#define LORARegModemConfig3                        0x26\r\n#define FSKRegPreambleLsb                          0x26\r\n#define FSKRegSyncConfig                           0x27\r\n#define LORARegFeiMsb                              0x28\r\n#define FSKRegSyncValue1                           0x28\r\n#define LORAFeiMib                                 0x29\r\n#define FSKRegSyncValue2                           0x29\r\n#define LORARegFeiLsb                              0x2A\r\n#define FSKRegSyncValue3                           0x2A\r\n#define FSKRegSyncValue4                           0x2B\r\n#define LORARegRssiWideband                        0x2C\r\n#define FSKRegSyncValue5                           0x2C\r\n#define FSKRegSyncValue6                           0x2D\r\n#define FSKRegSyncValue7                           0x2E\r\n#define FSKRegSyncValue8                           0x2F\r\n#define FSKRegPacketConfig1                        0x30\r\n#define FSKRegPacketConfig2                        0x31\r\n#define LORARegDetectOptimize                      0x31\r\n#define FSKRegPayloadLength                        0x32\r\n#define FSKRegNodeAdrs                             0x33\r\n#define LORARegInvertIQ                            0x33\r\n#define FSKRegBroadcastAdrs                        0x34\r\n#define FSKRegFifoThresh                           0x35\r\n#define FSKRegSeqConfig1                           0x36\r\n#define FSKRegSeqConfig2                           0x37\r\n#define LORARegDetectionThreshold                  0x37\r\n#define FSKRegTimerResol                           0x38\r\n#define FSKRegTimer1Coef                           0x39\r\n#define LORARegSyncWord                            0x39\r\n#define FSKRegTimer2Coef                           0x3A\r\n#define FSKRegImageCal                             0x3B\r\n#define FSKRegTemp                                 0x3C\r\n#define FSKRegLowBat                               0x3D\r\n#define FSKRegIrqFlags1                            0x3E\r\n#define FSKRegIrqFlags2                            0x3F\r\n#define RegDioMapping1                             0x40 // common\r\n#define RegDioMapping2                             0x41 // common\r\n#define RegVersion                                 0x42 // common\r\n// #define RegAgcRef                                  0x43 // common\r\n// #define RegAgcThresh1                              0x44 // common\r\n// #define RegAgcThresh2                              0x45 // common\r\n// #define RegAgcThresh3                              0x46 // common\r\n// #define RegPllHop                                  0x4B // common\r\n// #define RegTcxo                                    0x58 // common\r\n#define RegPaDac                                   0x5A // common\r\n// #define RegPll                                     0x5C // common\r\n// #define RegPllLowPn                                0x5E // common\r\n// #define RegFormerTemp                              0x6C // common\r\n// #define RegBitRateFrac                             0x70 // common\r\n\r\n// ----------------------------------------\r\n// spread factors and mode for RegModemConfig2\r\n#define SX1272_MC2_FSK  0x00\r\n#define SX1272_MC2_SF7  0x70\r\n#define SX1272_MC2_SF8  0x80\r\n#define SX1272_MC2_SF9  0x90\r\n#define SX1272_MC2_SF10 0xA0\r\n#define SX1272_MC2_SF11 0xB0\r\n#define SX1272_MC2_SF12 0xC0\r\n// bandwidth for RegModemConfig1\r\n#define SX1272_MC1_BW_125  0x00\r\n#define SX1272_MC1_BW_250  0x40\r\n#define SX1272_MC1_BW_500  0x80\r\n// coding rate for RegModemConfig1\r\n#define SX1272_MC1_CR_4_5 0x08\r\n#define SX1272_MC1_CR_4_6 0x10\r\n#define SX1272_MC1_CR_4_7 0x18\r\n#define SX1272_MC1_CR_4_8 0x20\r\n#define SX1272_MC1_IMPLICIT_HEADER_MODE_ON 0x04 // required for receive\r\n#define SX1272_MC1_RX_PAYLOAD_CRCON        0x02\r\n#define SX1272_MC1_LOW_DATA_RATE_OPTIMIZE  0x01 // mandated for SF11 and SF12\r\n// transmit power configuration for RegPaConfig\r\n#define SX1272_PAC_PA_SELECT_PA_BOOST 0x80\r\n#define SX1272_PAC_PA_SELECT_RFIO_PIN 0x00\r\n\r\n\r\n// sx1276 RegModemConfig1\r\n#define SX1276_MC1_BW_125                0x70\r\n#define SX1276_MC1_BW_250                0x80\r\n#define SX1276_MC1_BW_500                0x90\r\n#define SX1276_MC1_CR_4_5            0x02\r\n#define SX1276_MC1_CR_4_6            0x04\r\n#define SX1276_MC1_CR_4_7            0x06\r\n#define SX1276_MC1_CR_4_8            0x08\r\n\r\n#define SX1276_MC1_IMPLICIT_HEADER_MODE_ON    0x01\r\n\r\n// sx1276 RegModemConfig2\r\n#define SX1276_MC2_RX_PAYLOAD_CRCON        0x04\r\n\r\n// sx1276 RegModemConfig3\r\n#define SX1276_MC3_LOW_DATA_RATE_OPTIMIZE  0x08\r\n#define SX1276_MC3_AGCAUTO                 0x04\r\n\r\n// preamble for lora networks (nibbles swapped)\r\n#define LORA_MAC_PREAMBLE                  0x34\r\n\r\n#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1 0x0A\r\n#ifdef CFG_sx1276_radio\r\n#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x70\r\n#elif CFG_sx1272_radio\r\n#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x74\r\n#endif\r\n\r\n\r\n\r\n// ----------------------------------------\r\n// Constants for radio registers\r\n#define OPMODE_LORA      0x80\r\n#define OPMODE_MASK      0x07\r\n#define OPMODE_SLEEP     0x00\r\n#define OPMODE_STANDBY   0x01\r\n#define OPMODE_FSTX      0x02\r\n#define OPMODE_TX        0x03\r\n#define OPMODE_FSRX      0x04\r\n#define OPMODE_RX        0x05\r\n#define OPMODE_RX_SINGLE 0x06\r\n#define OPMODE_CAD       0x07\r\n\r\n// ----------------------------------------\r\n// Bits masking the corresponding IRQs from the radio\r\n#define IRQ_LORA_RXTOUT_MASK 0x80\r\n#define IRQ_LORA_RXDONE_MASK 0x40\r\n#define IRQ_LORA_CRCERR_MASK 0x20\r\n#define IRQ_LORA_HEADER_MASK 0x10\r\n#define IRQ_LORA_TXDONE_MASK 0x08\r\n#define IRQ_LORA_CDDONE_MASK 0x04\r\n#define IRQ_LORA_FHSSCH_MASK 0x02\r\n#define IRQ_LORA_CDDETD_MASK 0x01\r\n\r\n#define IRQ_FSK1_MODEREADY_MASK         0x80\r\n#define IRQ_FSK1_RXREADY_MASK           0x40\r\n#define IRQ_FSK1_TXREADY_MASK           0x20\r\n#define IRQ_FSK1_PLLLOCK_MASK           0x10\r\n#define IRQ_FSK1_RSSI_MASK              0x08\r\n#define IRQ_FSK1_TIMEOUT_MASK           0x04\r\n#define IRQ_FSK1_PREAMBLEDETECT_MASK    0x02\r\n#define IRQ_FSK1_SYNCADDRESSMATCH_MASK  0x01\r\n#define IRQ_FSK2_FIFOFULL_MASK          0x80\r\n#define IRQ_FSK2_FIFOEMPTY_MASK         0x40\r\n#define IRQ_FSK2_FIFOLEVEL_MASK         0x20\r\n#define IRQ_FSK2_FIFOOVERRUN_MASK       0x10\r\n#define IRQ_FSK2_PACKETSENT_MASK        0x08\r\n#define IRQ_FSK2_PAYLOADREADY_MASK      0x04\r\n#define IRQ_FSK2_CRCOK_MASK             0x02\r\n#define IRQ_FSK2_LOWBAT_MASK            0x01\r\n\r\n// ----------------------------------------\r\n// DIO function mappings                D0D1D2D3\r\n#define MAP_DIO0_LORA_RXDONE   0x00  // 00------\r\n#define MAP_DIO0_LORA_TXDONE   0x40  // 01------\r\n#define MAP_DIO1_LORA_RXTOUT   0x00  // --00----\r\n#define MAP_DIO1_LORA_NOP      0x30  // --11----\r\n#define MAP_DIO2_LORA_NOP      0xC0  // ----11--\r\n\r\n#define MAP_DIO0_FSK_READY     0x00  // 00------ (packet sent / payload ready)\r\n#define MAP_DIO1_FSK_NOP       0x30  // --11----\r\n#define MAP_DIO2_FSK_TXNOP     0x04  // ----01--\r\n#define MAP_DIO2_FSK_TIMEOUT   0x08  // ----10--\r\n\r\n\r\n// FSK IMAGECAL defines\r\n#define RF_IMAGECAL_AUTOIMAGECAL_MASK               0x7F\r\n#define RF_IMAGECAL_AUTOIMAGECAL_ON                 0x80\r\n#define RF_IMAGECAL_AUTOIMAGECAL_OFF                0x00  // Default\r\n\r\n#define RF_IMAGECAL_IMAGECAL_MASK                   0xBF\r\n#define RF_IMAGECAL_IMAGECAL_START                  0x40\r\n\r\n#define RF_IMAGECAL_IMAGECAL_RUNNING                0x20\r\n#define RF_IMAGECAL_IMAGECAL_DONE                   0x00  // Default\r\n\r\n\r\n// RADIO STATE\r\n// (initialized by radio_init(), used by radio_rand1())\r\nstatic u1_t randbuf[16];\r\n\r\n\r\n#ifdef CFG_sx1276_radio\r\n#define LNA_RX_GAIN (0x20|0x1)\r\n#elif CFG_sx1272_radio\r\n#define LNA_RX_GAIN (0x20|0x03)\r\n#else\r\n#error Missing CFG_sx1272_radio/CFG_sx1276_radio\r\n#endif\r\n\r\n\r\nstatic void writeReg (u1_t addr, u1_t data ) {\r\n    hal_pin_nss(0);\r\n    hal_spi(addr | 0x80);\r\n    hal_spi(data);\r\n    hal_pin_nss(1);\r\n}\r\n\r\nstatic u1_t readReg (u1_t addr) {\r\n    hal_pin_nss(0);\r\n    hal_spi(addr & 0x7F);\r\n    u1_t val = hal_spi(0x00);\r\n    hal_pin_nss(1);\r\n    return val;\r\n}\r\n\r\nstatic void writeBuf (u1_t addr, xref2u1_t buf, u1_t len) {\r\n    hal_pin_nss(0);\r\n    hal_spi(addr | 0x80);\r\n    for (u1_t i=0; i<len; i++) {\r\n        hal_spi(buf[i]);\r\n    }\r\n    hal_pin_nss(1);\r\n}\r\n\r\nstatic void readBuf (u1_t addr, xref2u1_t buf, u1_t len) {\r\n    hal_pin_nss(0);\r\n    hal_spi(addr & 0x7F);\r\n    for (u1_t i=0; i<len; i++) {\r\n        buf[i] = hal_spi(0x00);\r\n    }\r\n    hal_pin_nss(1);\r\n}\r\n\r\nstatic void opmode (u1_t mode) {\r\n    writeReg(RegOpMode, (readReg(RegOpMode) & ~OPMODE_MASK) | mode);\r\n}\r\n\r\nstatic void opmodeLora() {\r\n    u1_t u = OPMODE_LORA;\r\n#ifdef CFG_sx1276_radio\r\n    u |= 0x8;   // TBD: sx1276 high freq\r\n#endif\r\n    writeReg(RegOpMode, u);\r\n}\r\n\r\nstatic void opmodeFSK() {\r\n    u1_t u = 0;\r\n#ifdef CFG_sx1276_radio\r\n    u |= 0x8;   // TBD: sx1276 high freq\r\n#endif\r\n    writeReg(RegOpMode, u);\r\n}\r\n\r\n// configure LoRa modem (cfg1, cfg2)\r\nstatic void configLoraModem () {\r\n    sf_t sf = getSf(LMIC.rps);\r\n\r\n#ifdef CFG_sx1276_radio\r\n        u1_t mc1 = 0, mc2 = 0, mc3 = 0;\r\n\r\n        switch (getBw(LMIC.rps)) {\r\n        case BW125: mc1 |= SX1276_MC1_BW_125; break;\r\n        case BW250: mc1 |= SX1276_MC1_BW_250; break;\r\n        case BW500: mc1 |= SX1276_MC1_BW_500; break;\r\n        default:\r\n            ASSERT(0);\r\n        }\r\n        switch( getCr(LMIC.rps) ) {\r\n        case CR_4_5: mc1 |= SX1276_MC1_CR_4_5; break;\r\n        case CR_4_6: mc1 |= SX1276_MC1_CR_4_6; break;\r\n        case CR_4_7: mc1 |= SX1276_MC1_CR_4_7; break;\r\n        case CR_4_8: mc1 |= SX1276_MC1_CR_4_8; break;\r\n        default:\r\n            ASSERT(0);\r\n        }\r\n\r\n        if (getIh(LMIC.rps)) {\r\n            mc1 |= SX1276_MC1_IMPLICIT_HEADER_MODE_ON;\r\n            writeReg(LORARegPayloadLength, getIh(LMIC.rps)); // required length\r\n        }\r\n        // set ModemConfig1\r\n        writeReg(LORARegModemConfig1, mc1);\r\n\r\n        mc2 = (SX1272_MC2_SF7 + ((sf-1)<<4));\r\n        if (getNocrc(LMIC.rps) == 0) {\r\n            mc2 |= SX1276_MC2_RX_PAYLOAD_CRCON;\r\n        }\r\n        writeReg(LORARegModemConfig2, mc2);\r\n\r\n        mc3 = SX1276_MC3_AGCAUTO;\r\n        if ((sf == SF11 || sf == SF12) && getBw(LMIC.rps) == BW125) {\r\n            mc3 |= SX1276_MC3_LOW_DATA_RATE_OPTIMIZE;\r\n        }\r\n        writeReg(LORARegModemConfig3, mc3);\r\n#elif CFG_sx1272_radio\r\n        u1_t mc1 = (getBw(LMIC.rps)<<6);\r\n\r\n        switch( getCr(LMIC.rps) ) {\r\n        case CR_4_5: mc1 |= SX1272_MC1_CR_4_5; break;\r\n        case CR_4_6: mc1 |= SX1272_MC1_CR_4_6; break;\r\n        case CR_4_7: mc1 |= SX1272_MC1_CR_4_7; break;\r\n        case CR_4_8: mc1 |= SX1272_MC1_CR_4_8; break;\r\n        }\r\n\r\n        if ((sf == SF11 || sf == SF12) && getBw(LMIC.rps) == BW125) {\r\n            mc1 |= SX1272_MC1_LOW_DATA_RATE_OPTIMIZE;\r\n        }\r\n\r\n        if (getNocrc(LMIC.rps) == 0) {\r\n            mc1 |= SX1272_MC1_RX_PAYLOAD_CRCON;\r\n        }\r\n\r\n        if (getIh(LMIC.rps)) {\r\n            mc1 |= SX1272_MC1_IMPLICIT_HEADER_MODE_ON;\r\n            writeReg(LORARegPayloadLength, getIh(LMIC.rps)); // required length\r\n        }\r\n        // set ModemConfig1\r\n        writeReg(LORARegModemConfig1, mc1);\r\n\r\n        // set ModemConfig2 (sf, AgcAutoOn=1 SymbTimeoutHi=00)\r\n        writeReg(LORARegModemConfig2, (SX1272_MC2_SF7 + ((sf-1)<<4)) | 0x04);\r\n#else\r\n#error Missing CFG_sx1272_radio/CFG_sx1276_radio\r\n#endif /* CFG_sx1272_radio */\r\n}\r\n\r\nstatic void configChannel () {\r\n    // set frequency: FQ = (FRF * 32 Mhz) / (2 ^ 19)\r\n    uint64_t frf = ((uint64_t)LMIC.freq << 19) / 32000000;\r\n    writeReg(RegFrfMsb, (u1_t)(frf>>16));\r\n    writeReg(RegFrfMid, (u1_t)(frf>> 8));\r\n    writeReg(RegFrfLsb, (u1_t)(frf>> 0));\r\n}\r\n\r\n\r\n\r\nstatic void configPower () {\r\n#ifdef CFG_sx1276_radio\r\n    // no boost used for now\r\n    s1_t pw = (s1_t)LMIC.txpow;\r\n    if(pw >= 17) {\r\n        pw = 15;\r\n    } else if(pw < 2) {\r\n        pw = 2;\r\n    }\r\n    // check board type for BOOST pin\r\n    writeReg(RegPaConfig, (u1_t)(0x80|(pw&0xf)));\r\n    writeReg(RegPaDac, readReg(RegPaDac)|0x4);\r\n\r\n#elif CFG_sx1272_radio\r\n    // set PA config (2-17 dBm using PA_BOOST)\r\n    s1_t pw = (s1_t)LMIC.txpow;\r\n    if(pw > 17) {\r\n        pw = 17;\r\n    } else if(pw < 2) {\r\n        pw = 2;\r\n    }\r\n    writeReg(RegPaConfig, (u1_t)(0x80|(pw-2)));\r\n#else\r\n#error Missing CFG_sx1272_radio/CFG_sx1276_radio\r\n#endif /* CFG_sx1272_radio */\r\n}\r\n\r\nstatic void txfsk () {\r\n    // select FSK modem (from sleep mode)\r\n    writeReg(RegOpMode, 0x10); // FSK, BT=0.5\r\n    ASSERT(readReg(RegOpMode) == 0x10);\r\n    // enter standby mode (required for FIFO loading))\r\n    opmode(OPMODE_STANDBY);\r\n    // set bitrate\r\n    writeReg(FSKRegBitrateMsb, 0x02); // 50kbps\r\n    writeReg(FSKRegBitrateLsb, 0x80);\r\n    // set frequency deviation\r\n    writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz\r\n    writeReg(FSKRegFdevLsb, 0x99);\r\n    // frame and packet handler settings\r\n    writeReg(FSKRegPreambleMsb, 0x00);\r\n    writeReg(FSKRegPreambleLsb, 0x05);\r\n    writeReg(FSKRegSyncConfig, 0x12);\r\n    writeReg(FSKRegPacketConfig1, 0xD0);\r\n    writeReg(FSKRegPacketConfig2, 0x40);\r\n    writeReg(FSKRegSyncValue1, 0xC1);\r\n    writeReg(FSKRegSyncValue2, 0x94);\r\n    writeReg(FSKRegSyncValue3, 0xC1);\r\n    // configure frequency\r\n    configChannel();\r\n    // configure output power\r\n    configPower();\r\n\r\n    // set the IRQ mapping DIO0=PacketSent DIO1=NOP DIO2=NOP\r\n    writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TXNOP);\r\n\r\n    // initialize the payload size and address pointers\r\n    writeReg(FSKRegPayloadLength, LMIC.dataLen+1); // (insert length byte into payload))\r\n\r\n    // download length byte and buffer to the radio FIFO\r\n    writeReg(RegFifo, LMIC.dataLen);\r\n    writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);\r\n\r\n    // enable antenna switch for TX\r\n    hal_pin_rxtx(1);\r\n\r\n    // now we actually start the transmission\r\n    opmode(OPMODE_TX);\r\n}\r\n\r\nstatic void txlora () {\r\n    // select LoRa modem (from sleep mode)\r\n    //writeReg(RegOpMode, OPMODE_LORA);\r\n    opmodeLora();\r\n    ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);\r\n\r\n    // enter standby mode (required for FIFO loading))\r\n    opmode(OPMODE_STANDBY);\r\n    // configure LoRa modem (cfg1, cfg2)\r\n    configLoraModem();\r\n    // configure frequency\r\n    configChannel();\r\n    // configure output power\r\n    writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08); // set PA ramp-up time 50 uSec\r\n    configPower();\r\n    // set sync word\r\n    writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);\r\n\r\n    // set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP\r\n    writeReg(RegDioMapping1, MAP_DIO0_LORA_TXDONE|MAP_DIO1_LORA_NOP|MAP_DIO2_LORA_NOP);\r\n    // clear all radio IRQ flags\r\n    writeReg(LORARegIrqFlags, 0xFF);\r\n    // mask all IRQs but TxDone\r\n    writeReg(LORARegIrqFlagsMask, ~IRQ_LORA_TXDONE_MASK);\r\n\r\n    // initialize the payload size and address pointers\r\n    writeReg(LORARegFifoTxBaseAddr, 0x00);\r\n    writeReg(LORARegFifoAddrPtr, 0x00);\r\n    writeReg(LORARegPayloadLength, LMIC.dataLen);\r\n\r\n    // download buffer to the radio FIFO\r\n    writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);\r\n\r\n    // enable antenna switch for TX\r\n    hal_pin_rxtx(1);\r\n\r\n    // now we actually start the transmission\r\n    opmode(OPMODE_TX);\r\n\r\n#if LMIC_DEBUG_LEVEL > 0\r\n    u1_t sf = getSf(LMIC.rps) + 6; // 1 == SF7\r\n    u1_t bw = getBw(LMIC.rps);\r\n    u1_t cr = getCr(LMIC.rps);\r\n    printf(\"%lu: TXMODE, freq=%lu, len=%d, SF=%d, BW=%d, CR=4/%d, IH=%d\\n\",\r\n           os_getTime(), LMIC.freq, LMIC.dataLen, sf,\r\n           bw == BW125 ? 125 : (bw == BW250 ? 250 : 500),\r\n           cr == CR_4_5 ? 5 : (cr == CR_4_6 ? 6 : (cr == CR_4_7 ? 7 : 8)),\r\n           getIh(LMIC.rps)\r\n   );\r\n#endif\r\n}\r\n\r\n// start transmitter (buf=LMIC.frame, len=LMIC.dataLen)\r\nstatic void starttx () {\r\n    ASSERT( (readReg(RegOpMode) & OPMODE_MASK) == OPMODE_SLEEP );\r\n    if(getSf(LMIC.rps) == FSK) { // FSK modem\r\n        txfsk();\r\n    } else { // LoRa modem\r\n        txlora();\r\n    }\r\n    // the radio will go back to STANDBY mode as soon as the TX is finished\r\n    // the corresponding IRQ will inform us about completion.\r\n}\r\n\r\nenum { RXMODE_SINGLE, RXMODE_SCAN, RXMODE_RSSI };\r\n\r\nstatic CONST_TABLE(u1_t, rxlorairqmask)[] = {\r\n    [RXMODE_SINGLE] = IRQ_LORA_RXDONE_MASK|IRQ_LORA_RXTOUT_MASK,\r\n    [RXMODE_SCAN]   = IRQ_LORA_RXDONE_MASK,\r\n    [RXMODE_RSSI]   = 0x00,\r\n};\r\n\r\n// start LoRa receiver (time=LMIC.rxtime, timeout=LMIC.rxsyms, result=LMIC.frame[LMIC.dataLen])\r\nstatic void rxlora (u1_t rxmode) {\r\n    // select LoRa modem (from sleep mode)\r\n    opmodeLora();\r\n    ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);\r\n    // enter standby mode (warm up))\r\n    opmode(OPMODE_STANDBY);\r\n    // don't use MAC settings at startup\r\n    if(rxmode == RXMODE_RSSI) { // use fixed settings for rssi scan\r\n        writeReg(LORARegModemConfig1, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1);\r\n        writeReg(LORARegModemConfig2, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2);\r\n    } else { // single or continuous rx mode\r\n        // configure LoRa modem (cfg1, cfg2)\r\n        configLoraModem();\r\n        // configure frequency\r\n        configChannel();\r\n    }\r\n    // set LNA gain\r\n    writeReg(RegLna, LNA_RX_GAIN);\r\n    // set max payload size\r\n    writeReg(LORARegPayloadMaxLength, 64);\r\n#if !defined(DISABLE_INVERT_IQ_ON_RX)\r\n    // use inverted I/Q signal (prevent mote-to-mote communication)\r\n    writeReg(LORARegInvertIQ, readReg(LORARegInvertIQ)|(1<<6));\r\n#endif\r\n    // set symbol timeout (for single rx)\r\n    writeReg(LORARegSymbTimeoutLsb, LMIC.rxsyms);\r\n    // set sync word\r\n    writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);\r\n\r\n    // configure DIO mapping DIO0=RxDone DIO1=RxTout DIO2=NOP\r\n    writeReg(RegDioMapping1, MAP_DIO0_LORA_RXDONE|MAP_DIO1_LORA_RXTOUT|MAP_DIO2_LORA_NOP);\r\n    // clear all radio IRQ flags\r\n    writeReg(LORARegIrqFlags, 0xFF);\r\n    // enable required radio IRQs\r\n    writeReg(LORARegIrqFlagsMask, ~TABLE_GET_U1(rxlorairqmask, rxmode));\r\n\r\n    // enable antenna switch for RX\r\n    hal_pin_rxtx(0);\r\n\r\n    // now instruct the radio to receive\r\n    if (rxmode == RXMODE_SINGLE) { // single rx\r\n        hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time\r\n        opmode(OPMODE_RX_SINGLE);\r\n    } else { // continous rx (scan or rssi)\r\n        opmode(OPMODE_RX);\r\n    }\r\n\r\n#if LMIC_DEBUG_LEVEL > 0\r\n    if (rxmode == RXMODE_RSSI) {\r\n        printf(\"RXMODE_RSSI\\n\");\r\n    } else {\r\n        u1_t sf = getSf(LMIC.rps) + 6; // 1 == SF7\r\n        u1_t bw = getBw(LMIC.rps);\r\n        u1_t cr = getCr(LMIC.rps);\r\n        printf(\"%lu: %s, freq=%lu, SF=%d, BW=%d, CR=4/%d, IH=%d\\n\",\r\n               os_getTime(),\r\n               rxmode == RXMODE_SINGLE ? \"RXMODE_SINGLE\" : (rxmode == RXMODE_SCAN ? \"RXMODE_SCAN\" : \"UNKNOWN_RX\"),\r\n               LMIC.freq, sf,\r\n               bw == BW125 ? 125 : (bw == BW250 ? 250 : 500),\r\n               cr == CR_4_5 ? 5 : (cr == CR_4_6 ? 6 : (cr == CR_4_7 ? 7 : 8)),\r\n               getIh(LMIC.rps)\r\n       );\r\n    }\r\n#endif\r\n}\r\n\r\nstatic void rxfsk (u1_t rxmode) {\r\n    // only single rx (no continuous scanning, no noise sampling)\r\n    ASSERT( rxmode == RXMODE_SINGLE );\r\n    // select FSK modem (from sleep mode)\r\n    //writeReg(RegOpMode, 0x00); // (not LoRa)\r\n    opmodeFSK();\r\n    ASSERT((readReg(RegOpMode) & OPMODE_LORA) == 0);\r\n    // enter standby mode (warm up))\r\n    opmode(OPMODE_STANDBY);\r\n    // configure frequency\r\n    configChannel();\r\n    // set LNA gain\r\n    //writeReg(RegLna, 0x20|0x03); // max gain, boost enable\r\n    writeReg(RegLna, LNA_RX_GAIN);\r\n    // configure receiver\r\n    writeReg(FSKRegRxConfig, 0x1E); // AFC auto, AGC, trigger on preamble?!?\r\n    // set receiver bandwidth\r\n    writeReg(FSKRegRxBw, 0x0B); // 50kHz SSb\r\n    // set AFC bandwidth\r\n    writeReg(FSKRegAfcBw, 0x12); // 83.3kHz SSB\r\n    // set preamble detection\r\n    writeReg(FSKRegPreambleDetect, 0xAA); // enable, 2 bytes, 10 chip errors\r\n    // set sync config\r\n    writeReg(FSKRegSyncConfig, 0x12); // no auto restart, preamble 0xAA, enable, fill FIFO, 3 bytes sync\r\n    // set packet config\r\n    writeReg(FSKRegPacketConfig1, 0xD8); // var-length, whitening, crc, no auto-clear, no adr filter\r\n    writeReg(FSKRegPacketConfig2, 0x40); // packet mode\r\n    // set sync value\r\n    writeReg(FSKRegSyncValue1, 0xC1);\r\n    writeReg(FSKRegSyncValue2, 0x94);\r\n    writeReg(FSKRegSyncValue3, 0xC1);\r\n    // set preamble timeout\r\n    writeReg(FSKRegRxTimeout2, 0xFF);//(LMIC.rxsyms+1)/2);\r\n    // set bitrate\r\n    writeReg(FSKRegBitrateMsb, 0x02); // 50kbps\r\n    writeReg(FSKRegBitrateLsb, 0x80);\r\n    // set frequency deviation\r\n    writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz\r\n    writeReg(FSKRegFdevLsb, 0x99);\r\n\r\n    // configure DIO mapping DIO0=PayloadReady DIO1=NOP DIO2=TimeOut\r\n    writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TIMEOUT);\r\n\r\n    // enable antenna switch for RX\r\n    hal_pin_rxtx(0);\r\n\r\n    // now instruct the radio to receive\r\n    hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time\r\n    opmode(OPMODE_RX); // no single rx mode available in FSK\r\n}\r\n\r\nstatic void startrx (u1_t rxmode) {\r\n    ASSERT( (readReg(RegOpMode) & OPMODE_MASK) == OPMODE_SLEEP );\r\n    if(getSf(LMIC.rps) == FSK) { // FSK modem\r\n        rxfsk(rxmode);\r\n    } else { // LoRa modem\r\n        rxlora(rxmode);\r\n    }\r\n    // the radio will go back to STANDBY mode as soon as the RX is finished\r\n    // or timed out, and the corresponding IRQ will inform us about completion.\r\n}\r\n\r\n// get random seed from wideband noise rssi\r\nvoid radio_init () {\r\n    hal_disableIRQs();\r\n\r\n    // manually reset radio\r\n#ifdef CFG_sx1276_radio\r\n    hal_pin_rst(0); // drive RST pin low\r\n#else\r\n    hal_pin_rst(1); // drive RST pin high\r\n#endif\r\n    hal_waitUntil(os_getTime()+ms2osticks(1)); // wait >100us\r\n    hal_pin_rst(2); // configure RST pin floating!\r\n    hal_waitUntil(os_getTime()+ms2osticks(5)); // wait 5ms\r\n\r\n    opmode(OPMODE_SLEEP);\r\n\r\n    // some sanity checks, e.g., read version number\r\n    u1_t v = readReg(RegVersion);\r\n#ifdef CFG_sx1276_radio\r\n    ASSERT(v == 0x12 );\r\n#elif CFG_sx1272_radio\r\n    ASSERT(v == 0x22);\r\n#else\r\n#error Missing CFG_sx1272_radio/CFG_sx1276_radio\r\n#endif\r\n    // seed 15-byte randomness via noise rssi\r\n    rxlora(RXMODE_RSSI);\r\n    while( (readReg(RegOpMode) & OPMODE_MASK) != OPMODE_RX ); // continuous rx\r\n    for(int i=1; i<16; i++) {\r\n        for(int j=0; j<8; j++) {\r\n            u1_t b; // wait for two non-identical subsequent least-significant bits\r\n            while( (b = readReg(LORARegRssiWideband) & 0x01) == (readReg(LORARegRssiWideband) & 0x01) );\r\n            randbuf[i] = (randbuf[i] << 1) | b;\r\n        }\r\n    }\r\n    randbuf[0] = 16; // set initial index\r\n\r\n#ifdef CFG_sx1276mb1_board\r\n    // chain calibration\r\n    writeReg(RegPaConfig, 0);\r\n\r\n    // Launch Rx chain calibration for LF band\r\n    writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);\r\n    while((readReg(FSKRegImageCal)&RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING){ ; }\r\n\r\n    // Sets a Frequency in HF band\r\n    u4_t frf = 868000000;\r\n    writeReg(RegFrfMsb, (u1_t)(frf>>16));\r\n    writeReg(RegFrfMid, (u1_t)(frf>> 8));\r\n    writeReg(RegFrfLsb, (u1_t)(frf>> 0));\r\n\r\n    // Launch Rx chain calibration for HF band\r\n    writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);\r\n    while((readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING) { ; }\r\n#endif /* CFG_sx1276mb1_board */\r\n\r\n    opmode(OPMODE_SLEEP);\r\n\r\n    hal_enableIRQs();\r\n}\r\n\r\n// return next random byte derived from seed buffer\r\n// (buf[0] holds index of next byte to be returned)\r\nu1_t radio_rand1 () {\r\n    u1_t i = randbuf[0];\r\n    ASSERT( i != 0 );\r\n    if( i==16 ) {\r\n        os_aes(AES_ENC, randbuf, 16); // encrypt seed with any key\r\n        i = 0;\r\n    }\r\n    u1_t v = randbuf[i++];\r\n    randbuf[0] = i;\r\n    return v;\r\n}\r\n\r\nu1_t radio_rssi () {\r\n    hal_disableIRQs();\r\n    u1_t r = readReg(LORARegRssiValue);\r\n    hal_enableIRQs();\r\n    return r;\r\n}\r\n\r\nstatic CONST_TABLE(u2_t, LORA_RXDONE_FIXUP)[] = {\r\n    [FSK]  =     us2osticks(0), // (   0 ticks)\r\n    [SF7]  =     us2osticks(0), // (   0 ticks)\r\n    [SF8]  =  us2osticks(1648), // (  54 ticks)\r\n    [SF9]  =  us2osticks(3265), // ( 107 ticks)\r\n    [SF10] =  us2osticks(7049), // ( 231 ticks)\r\n    [SF11] = us2osticks(13641), // ( 447 ticks)\r\n    [SF12] = us2osticks(31189), // (1022 ticks)\r\n};\r\n\r\n// called by hal ext IRQ handler\r\n// (radio goes to stanby mode after tx/rx operations)\r\nvoid radio_irq_handler (u1_t dio) {\r\n    ostime_t now = os_getTime();\r\n    if( (readReg(RegOpMode) & OPMODE_LORA) != 0) { // LORA modem\r\n        u1_t flags = readReg(LORARegIrqFlags);\r\n        if( flags & IRQ_LORA_TXDONE_MASK ) {\r\n            // save exact tx time\r\n            LMIC.txend = now - us2osticks(43); // TXDONE FIXUP\r\n        } else if( flags & IRQ_LORA_RXDONE_MASK ) {\r\n            // save exact rx time\r\n            if(getBw(LMIC.rps) == BW125) {\r\n                now -= TABLE_GET_U2(LORA_RXDONE_FIXUP, getSf(LMIC.rps));\r\n            }\r\n            LMIC.rxtime = now;\r\n            // read the PDU and inform the MAC that we received something\r\n            LMIC.dataLen = (readReg(LORARegModemConfig1) & SX1272_MC1_IMPLICIT_HEADER_MODE_ON) ?\r\n                readReg(LORARegPayloadLength) : readReg(LORARegRxNbBytes);\r\n            // set FIFO read address pointer\r\n            writeReg(LORARegFifoAddrPtr, readReg(LORARegFifoRxCurrentAddr));\r\n            // now read the FIFO\r\n            readBuf(RegFifo, LMIC.frame, LMIC.dataLen);\r\n            // read rx quality parameters\r\n            LMIC.snr  = readReg(LORARegPktSnrValue); // SNR [dB] * 4\r\n            LMIC.rssi = readReg(LORARegPktRssiValue) - 125 + 64; // RSSI [dBm] (-196...+63)\r\n        } else if( flags & IRQ_LORA_RXTOUT_MASK ) {\r\n            // indicate timeout\r\n            LMIC.dataLen = 0;\r\n        }\r\n        // mask all radio IRQs\r\n        writeReg(LORARegIrqFlagsMask, 0xFF);\r\n        // clear radio IRQ flags\r\n        writeReg(LORARegIrqFlags, 0xFF);\r\n    } else { // FSK modem\r\n        u1_t flags1 = readReg(FSKRegIrqFlags1);\r\n        u1_t flags2 = readReg(FSKRegIrqFlags2);\r\n        if( flags2 & IRQ_FSK2_PACKETSENT_MASK ) {\r\n            // save exact tx time\r\n            LMIC.txend = now;\r\n        } else if( flags2 & IRQ_FSK2_PAYLOADREADY_MASK ) {\r\n            // save exact rx time\r\n            LMIC.rxtime = now;\r\n            // read the PDU and inform the MAC that we received something\r\n            LMIC.dataLen = readReg(FSKRegPayloadLength);\r\n            // now read the FIFO\r\n            readBuf(RegFifo, LMIC.frame, LMIC.dataLen);\r\n            // read rx quality parameters\r\n            LMIC.snr  = 0; // determine snr\r\n            LMIC.rssi = 0; // determine rssi\r\n        } else if( flags1 & IRQ_FSK1_TIMEOUT_MASK ) {\r\n            // indicate timeout\r\n            LMIC.dataLen = 0;\r\n        } else {\r\n            ASSERT(0);\r\n        }\r\n    }\r\n    // go from stanby to sleep\r\n    opmode(OPMODE_SLEEP);\r\n    // run os job (use preset func ptr)\r\n    os_setCallback(&LMIC.osjob, LMIC.osjob.func);\r\n}\r\n\r\nvoid os_radio (u1_t mode) {\r\n    hal_disableIRQs();\r\n    switch (mode) {\r\n      case RADIO_RST:\r\n        // put radio to sleep\r\n        opmode(OPMODE_SLEEP);\r\n        break;\r\n\r\n      case RADIO_TX:\r\n        // transmit frame now\r\n        starttx(); // buf=LMIC.frame, len=LMIC.dataLen\r\n        break;\r\n\r\n      case RADIO_RX:\r\n        // receive frame now (exactly at rxtime)\r\n        startrx(RXMODE_SINGLE); // buf=LMIC.frame, time=LMIC.rxtime, timeout=LMIC.rxsyms\r\n        break;\r\n\r\n      case RADIO_RXON:\r\n        // start scanning for beacon now\r\n        startrx(RXMODE_SCAN); // buf=LMIC.frame\r\n        break;\r\n    }\r\n    hal_enableIRQs();\r\n}\r\n\r\n\r\nconfig.h file which i am using \r\n#ifndef _lmic_config_h_\r\n#define _lmic_config_h_\r\n\r\n// In the original LMIC code, these config values were defined on the\r\n// gcc commandline. Since Arduino does not allow easily modifying the\r\n// compiler commandline, use this file instead.\r\n\r\n#define CFG_eu868 1\r\n//#define CFG_us915 1\r\n// This is the SX1272/SX1273 radio, which is also used on the HopeRF\r\n// RFM92 boards.\r\n//#define CFG_sx1272_radio 1\r\n// This is the SX1276/SX1277/SX1278/SX1279 radio, which is also used on\r\n// the HopeRF RFM95 boards.\r\n#define CFG_sx1276_radio 1\r\n\r\n// 16 μs per tick\r\n// LMIC requires ticks to be 15.5μs - 100 μs long\r\n#define US_PER_OSTICK_EXPONENT 4\r\n#define US_PER_OSTICK (1 << US_PER_OSTICK_EXPONENT)\r\n#define OSTICKS_PER_SEC (1000000 / US_PER_OSTICK)\r\n\r\n// Set this to 1 to enable some basic debug output (using printf) about\r\n// RF settings used during transmission and reception. Set to 2 to\r\n// enable more verbose output. Make sure that printf is actually\r\n// configured (e.g. on AVR it is not by default), otherwise using it can\r\n// cause crashing.\r\n#define LMIC_DEBUG_LEVEL 0\r\n\r\n// Enable this to allow using printf() to print to the given serial port\r\n// (or any other Print object). This can be easy for debugging. The\r\n// current implementation only works on AVR, though.\r\n//#define LMIC_PRINTF_TO Serial\r\n\r\n// Any runtime assertion failures are printed to this serial port (or\r\n// any other Print object). If this is unset, any failures just silently\r\n// halt execution.\r\n#define LMIC_FAILURE_TO Serial\r\n\r\n// Uncomment this to disable all code related to joining\r\n//#define DISABLE_JOIN\r\n// Uncomment this to disable all code related to ping\r\n//#define DISABLE_PING\r\n// Uncomment this to disable all code related to beacon tracking.\r\n// Requires ping to be disabled too\r\n//#define DISABLE_BEACONS\r\n\r\n// Uncomment these to disable the corresponding MAC commands.\r\n// Class A\r\n//#define DISABLE_MCMD_DCAP_REQ // duty cycle cap\r\n//#define DISABLE_MCMD_DN2P_SET // 2nd DN window param\r\n//#define DISABLE_MCMD_SNCH_REQ // set new channel\r\n// Class B\r\n//#define DISABLE_MCMD_PING_SET // set ping freq, automatically disabled by DISABLE_PING\r\n//#define DISABLE_MCMD_BCNI_ANS // next beacon start, automatical disabled by DISABLE_BEACON\r\n\r\n// In LoRaWAN, a gateway applies I/Q inversion on TX, and nodes do the\r\n// same on RX. This ensures that gateways can talk to nodes and vice\r\n// versa, but gateways will not hear other gateways and nodes will not\r\n// hear other nodes. By uncommenting this macro, this inversion is\r\n// disabled and this node can hear other nodes. If two nodes both have\r\n// this macro set, they can talk to each other (but they can no longer\r\n// hear gateways). This should probably only be used when debugging\r\n// and/or when talking to the radio directly (e.g. like in the \"raw\"\r\n// example).\r\n//#define DISABLE_INVERT_IQ_ON_RX\r\n\r\n// This allows choosing between multiple included AES implementations.\r\n// Make sure exactly one of these is uncommented.\r\n//\r\n// This selects the original AES implementation included LMIC. This\r\n// implementation is optimized for speed on 32-bit processors using\r\n// fairly big lookup tables, but it takes up big amounts of flash on the\r\n// AVR architecture.\r\n// #define USE_ORIGINAL_AES\r\n//\r\n// This selects the AES implementation written by Ideetroon for their\r\n// own LoRaWAN library. It also uses lookup tables, but smaller\r\n// byte-oriented ones, making it use a lot less flash space (but it is\r\n// also about twice as slow as the original).\r\n#define USE_IDEETRON_AES\r\n\r\n#endif // _lmic_config_h_\r\n"},"comment":{"url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/comments/280552341","html_url":"https://github.com/matthijskooijman/arduino-lmic/issues/68#issuecomment-280552341","issue_url":"https://api.github.com/repos/matthijskooijman/arduino-lmic/issues/68","id":280552341,"user":{"login":"cattvm","id":4123647,"avatar_url":"https://avatars.githubusercontent.com/u/4123647?v=3","gravatar_id":"","url":"https://api.github.com/users/cattvm","html_url":"https://github.com/cattvm","followers_url":"https://api.github.com/users/cattvm/followers","following_url":"https://api.github.com/users/cattvm/following{/other_user}","gists_url":"https://api.github.com/users/cattvm/gists{/gist_id}","starred_url":"https://api.github.com/users/cattvm/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cattvm/subscriptions","organizations_url":"https://api.github.com/users/cattvm/orgs","repos_url":"https://api.github.com/users/cattvm/repos","events_url":"https://api.github.com/users/cattvm/events{/privacy}","received_events_url":"https://api.github.com/users/cattvm/received_events","type":"User","site_admin":false},"created_at":"2017-02-17T04:55:27Z","updated_at":"2017-02-17T04:55:27Z","body":"Hi Ramesh,\n\nIt's the problem with your hardware connection with SX1276, nothing else.\nThe error point to the line where it can read actual pin. Check power\nsupply, GND with voltmeter at sx1276.\n\nCan u please share your PIN mapping code with Ur Arudino to SX1276 wire\nconnection.\n\nDo a things, try to write a code only for DIO0,1,2 pins with LED blinking\nand see it led is blinking.\n\nIf Led is blinking then Ur naming to DIO0,1,2 is correct or else check pin\nnaming.\n\nOn 17-Feb-2017 01:57, \"Oliv4945\" <notifications@github.com> wrote:\n\n> Dear,\n>\n> What hardware do you use ? If you doubled checked the pin mapping\n> <https://github.com/matthijskooijman/arduino-lmic#pin-mapping> and radio\n> declaration\n> <https://github.com/matthijskooijman/arduino-lmic/blob/master/src/lmic/config.h#L12>,\n> you can slow the SPI communication on this line\n> <https://github.com/matthijskooijman/arduino-lmic/blob/master/src/hal/hal.cpp#L77>\n> to 2 MHz (2E6) , see #9\n> <https://github.com/matthijskooijman/arduino-lmic/issues/9> for info.\n>\n> —\n> You are receiving this because you are subscribed to this thread.\n> Reply to this email directly, view it on GitHub\n> <https://github.com/matthijskooijman/arduino-lmic/issues/68#issuecomment-280449500>,\n> or mute the thread\n> <https://github.com/notifications/unsubscribe-auth/AD7r_zoV69H3Ogr9_slHEIL7tlkrTLb7ks5rdLEogaJpZM4MC4xn>\n> .\n>\n"}}
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