{"push_id":1637391523,"size":11,"distinct_size":11,"ref":"refs/heads/master","head":"424b6898c8b24f7e89d2c13a141914984ce0f886","before":"d07c6f46c441c32c55076a45479530707170c55c","commits":[{"sha":"ac8616e4c81dded650dfade49a7da283565d37ce","author":{"name":"Chen-Yu Tsai","email":"d935d34b7d281e4f50030b838a1bf5c8f10bdb43@csie.org"},"message":"clk: sunxi-ng: mp: Adjust parent rate for pre-dividers\n\nThe MP style clocks support an mux with pre-dividers. While the driver\ncorrectly accounted for them in the .determine_rate callback, it did\nnot in the .recalc_rate and .set_rate callbacks.\n\nThis means when calculating the factors in the .set_rate callback, they\nwould be off by a factor of the active pre-divider. Same goes for\nreading back the clock rate after it is set.\n\nCc: stable@vger.kernel.org\nFixes: 2ab836db5097 (\"clk: sunxi-ng: Add M-P factor clock support\")\nSigned-off-by: Chen-Yu Tsai <wens@csie.org>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/ac8616e4c81dded650dfade49a7da283565d37ce"},{"sha":"69c9ae5041309553472ee798d7683be31bcdc434","author":{"name":"Arnd Bergmann","email":"72a0f6d3b182607e6d5c44b93e1abb7b23ee18f3@arndb.de"},"message":"clk: sunxi: ccu-sun5i needs nkmp\n\nA randconfig build ran into this rare link error:\n\ndrivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_nkmp_ops'\ndrivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.7+0x4): undefined reference to `ccu_nkmp_ops'\n\nThis adds the missing 'select'.\n\nFixes: 5e73761786d6 (\"clk: sunxi-ng: Add sun5i CCU driver\")\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/69c9ae5041309553472ee798d7683be31bcdc434"},{"sha":"9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d","author":{"name":"Chen-Yu Tsai","email":"d935d34b7d281e4f50030b838a1bf5c8f10bdb43@csie.org"},"message":"clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock\n\nThe enable bit offset for the hdmi-ddc module clock is wrong. It is\npointing to the main hdmi module clock enable bit.\n\nReported-by: Bob Ham <rah@settrans.net>\nFixes: c6e6c96d8fa6 (\"clk: sunxi-ng: Add A31/A31s clocks\")\nCc: stable@vger.kernel.org # 4.9.x-\nSigned-off-by: Chen-Yu Tsai <wens@csie.org>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d"},{"sha":"cda82ace3d4eff6a38f00a65db435fe35a3916f0","author":{"name":"Thomas Petazzoni","email":"8184181a894e706105679bbf6797daaadfd8a66a@free-electrons.com"},"message":"dt-bindings: arm: update Armada CP110 system controller binding\n\nIt turns out that in the CP110 HW block present in Marvell Armada\n7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the\nGOP block. This commit updates the Device Tree binding for this piece\nof hardware accordingly.\n\nSigned-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/cda82ace3d4eff6a38f00a65db435fe35a3916f0"},{"sha":"253160a8ad06bcc1c1db16a58b1f06d5128f6c5e","author":{"name":"Leonard Crestez","email":"f419bffefded4052ada67fd74a3c84ecc7fbe630@nxp.com"},"message":"clk: core: Copy connection id\n\nSome drivers use sprintf to build clk connection id names but the clk\ncore will save those strings and occasionally print them back. Duplicate\nthe con_id strings instead of fixing all the users.\n\nSigned-off-by: Leonard Crestez <leonard.crestez@nxp.com>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/253160a8ad06bcc1c1db16a58b1f06d5128f6c5e"},{"sha":"9b1b23f03abdd25ffde8bbfe5824b89bc0448c28","author":{"name":"Heiko Stuebner","email":"f67af7135bf5422071c7efd95ce8a74473489823@sntech.de"},"message":"clk: rockchip: add \",\" to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036\n\nThe mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a \",\"\nbetween the 3rd and 4th parent names, making them fall together and thus\nlookups fail. Fix that.\n\nFixes: 5190c08b2989 (\"clk: rockchip: add clock controller for rk3036\")\nSigned-off-by: Heiko Stuebner <heiko@sntech.de>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/9b1b23f03abdd25ffde8bbfe5824b89bc0448c28"},{"sha":"f8ba2d68e54fbca340ad0fce97397291ba9637bc","author":{"name":"Heiko Stuebner","email":"f67af7135bf5422071c7efd95ce8a74473489823@sntech.de"},"message":"clk: rockchip: Make uartpll a child of the gpll on rk3036\n\nThe shared uart-pll is on boot a child of the apll that can get changed\nby cpu frequency scaling. So move it away to the more stable gpll to\nmake sure the uart doesn't break on cpu frequency changes.\n\nThis turned up during the 4.11 merge-window when commit\n6a171b299379 (\"serial: 8250_dw: Allow hardware flow control to be used\")\nadded general termios enablement making the uart on rk3036 change\nfrequency and thus making it susceptible for the frequency scaling issue.\n\nSigned-off-by: Heiko Stuebner <heiko@sntech.de>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/f8ba2d68e54fbca340ad0fce97397291ba9637bc"},{"sha":"fe686babf4cf62b9b214b99847c735baa35a9fa2","author":{"name":"Philipp Tomsich","email":"340754537c69bbbf8cebf3559e80eed495e9c36d@theobroma-systems.com"},"message":"clk: sunxi-ng: Fix div/mult settings for osc12M on A64\n\nThe mult/div for osc12M was previously backwards (giving a 48M rate\nfor osc12M). Fix it.\n\nSigned-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nTested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/fe686babf4cf62b9b214b99847c735baa35a9fa2"},{"sha":"b467e08a15563dede0d37d3233baa24fb97a7310","author":{"name":"Icenowy Zheng","email":"64c40edd0dc04061a867cb569405127102951f02@aosc.xyz"},"message":"clk: sunxi-ng: fix recalc_rate formula of NKMP clocks\n\nIn commit e66f81bbd746 (\"clk: sunxi-ng: Implement factors offsets\"), the\nfinal formula of NKMP clocks' recalc_rate is refactored; however, the\nrefactored formula broke the calculation due to some C language operand\npriority problem -- the priority of operand >> is lower than * and /,\nmakes the formula being parsed as \"(parent_rate * n * k) >> (p / m)\", but\nit should be \"(parent_rate * n * k >> p) / m\".\n\nAdd the pair of parentheses to fix up this issue. This pair of\nparentheses used to exist in the old formula.\n\nFixes: e66f81bbd746 (\"clk: sunxi-ng: Implement factors offsets\")\nSigned-off-by: Icenowy Zheng <icenowy@aosc.xyz>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/b467e08a15563dede0d37d3233baa24fb97a7310"},{"sha":"7f0b97d5bb4c1c99c38dd6770ad11f714ea42583","author":{"name":"Stephen Boyd","email":"496892c5e989e3d4519358ac44c914f60a4d59d9@codeaurora.org"},"message":"Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes\n\nPull Allwinner clock fixes from Maxime Ripard:\n\nA few fixes for a bunch of clocks on a few SoCs. The most important one is\nprobably one that fixes the NKMP clock frequency calculation and could end\nup with clocking the CPU frequency to out of bounds rates.\n\n* tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:\n  clk: sunxi-ng: fix recalc_rate formula of NKMP clocks\n  clk: sunxi-ng: Fix div/mult settings for osc12M on A64\n  clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock\n  clk: sunxi: ccu-sun5i needs nkmp\n  clk: sunxi-ng: mp: Adjust parent rate for pre-dividers","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/7f0b97d5bb4c1c99c38dd6770ad11f714ea42583"},{"sha":"424b6898c8b24f7e89d2c13a141914984ce0f886","author":{"name":"Linus Torvalds","email":"ead7104581934751970e9decb2db5deb20a9e407@linux-foundation.org"},"message":"Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux\n\nPull clk fixes from Stephen Boyd:\n \"A handful of Sunxi and Rockchip clk driver fixes and a core framework\n  one where we need to copy a string because we can't guarantee it isn't\n  freed sometime later\"\n\n* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:\n  clk: sunxi-ng: fix recalc_rate formula of NKMP clocks\n  clk: sunxi-ng: Fix div/mult settings for osc12M on A64\n  clk: rockchip: Make uartpll a child of the gpll on rk3036\n  clk: rockchip: add \",\" to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036\n  clk: core: Copy connection id\n  dt-bindings: arm: update Armada CP110 system controller binding\n  clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock\n  clk: sunxi: ccu-sun5i needs nkmp\n  clk: sunxi-ng: mp: Adjust parent rate for pre-dividers","distinct":true,"url":"https://api.github.com/repos/moontide/linux/commits/424b6898c8b24f7e89d2c13a141914984ce0f886"}]}
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