{"action":"created","issue":{"url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/11","repository_url":"https://api.github.com/repos/tgingold/ghdlsynth-beta","labels_url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/11/labels{/name}","comments_url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/11/comments","events_url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/11/events","html_url":"https://github.com/tgingold/ghdlsynth-beta/issues/11","id":210258763,"number":11,"title":"ERROR: Unsupported instances of logic gates.","user":{"login":"C47D","id":11037705,"avatar_url":"https://avatars.githubusercontent.com/u/11037705?v=3","gravatar_id":"","url":"https://api.github.com/users/C47D","html_url":"https://github.com/C47D","followers_url":"https://api.github.com/users/C47D/followers","following_url":"https://api.github.com/users/C47D/following{/other_user}","gists_url":"https://api.github.com/users/C47D/gists{/gist_id}","starred_url":"https://api.github.com/users/C47D/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/C47D/subscriptions","organizations_url":"https://api.github.com/users/C47D/orgs","repos_url":"https://api.github.com/users/C47D/repos","events_url":"https://api.github.com/users/C47D/events{/privacy}","received_events_url":"https://api.github.com/users/C47D/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":4,"created_at":"2017-02-25T20:14:30Z","updated_at":"2017-02-27T01:23:42Z","closed_at":"2017-02-26T06:50:41Z","body":"Hi, thanks for the work you are doing. I'm implementing some very basic designs with VHDL for the iCEStick board, here's my code:\r\n``` vhdl\r\nlibrary ieee;\r\nuse ieee.std_logic_1164.all;\r\n\r\nentity test_or is port (\r\n    sel0, sel1: in std_logic;\r\n    c: out std_logic);\r\nend test_or;\r\n\r\narchitecture synth of test_or is\r\nbegin\r\n\r\n    c <= sel1 or sel0;\r\n\r\nend synth;\r\n```\r\n\r\nUsing the attached Makefile i get the following error:\r\n```\r\n$ make\r\nghdl -a test_or.vhdl\r\nyosys -q -m ~/ghdlsynth-beta/ghdl.so -p 'ghdl test_or; synth_ice40 -blif test_or.blif'\r\nERROR: Unsupported(1): instance \\test_or%1 of $or.\r\nMakefile:8: recipe for target 'test_or.blif' failed\r\nmake: *** [test_or.blif] Error 1\r\n```\r\n\r\nSearching on the ghdl.cc file of this repository seems like the or cell hasn't been implemented yet, the same error happens for xor gate.\r\n\r\nAny thoughts?\r\n\r\nThanks in advance\r\n- Carlos\r\n\r\n\r\n\r\n[or.zip](https://github.com/tgingold/ghdlsynth-beta/files/801463/or.zip)\r\n"},"comment":{"url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/comments/282606524","html_url":"https://github.com/tgingold/ghdlsynth-beta/issues/11#issuecomment-282606524","issue_url":"https://api.github.com/repos/tgingold/ghdlsynth-beta/issues/11","id":282606524,"user":{"login":"C47D","id":11037705,"avatar_url":"https://avatars.githubusercontent.com/u/11037705?v=3","gravatar_id":"","url":"https://api.github.com/users/C47D","html_url":"https://github.com/C47D","followers_url":"https://api.github.com/users/C47D/followers","following_url":"https://api.github.com/users/C47D/following{/other_user}","gists_url":"https://api.github.com/users/C47D/gists{/gist_id}","starred_url":"https://api.github.com/users/C47D/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/C47D/subscriptions","organizations_url":"https://api.github.com/users/C47D/orgs","repos_url":"https://api.github.com/users/C47D/repos","events_url":"https://api.github.com/users/C47D/events{/privacy}","received_events_url":"https://api.github.com/users/C47D/received_events","type":"User","site_admin":false},"created_at":"2017-02-27T01:23:42Z","updated_at":"2017-02-27T01:23:42Z","body":"Just tested all the basic gates, and, or, xor, nand, nor, not and xnor and all seems to be working properly.\r\n\r\nThanks again\r\nCarlos"}}
{"actor":{"display_login":"C47D"}}