{"action":"created","issue":{"url":"https://api.github.com/repos/EttusResearch/fpga/issues/16","repository_url":"https://api.github.com/repos/EttusResearch/fpga","labels_url":"https://api.github.com/repos/EttusResearch/fpga/issues/16/labels{/name}","comments_url":"https://api.github.com/repos/EttusResearch/fpga/issues/16/comments","events_url":"https://api.github.com/repos/EttusResearch/fpga/issues/16/events","html_url":"https://github.com/EttusResearch/fpga/pull/16","id":242756632,"number":16,"title":"Establish formal bit length of WINDOW_LEN","user":{"login":"tomberek","id":178444,"avatar_url":"https://avatars0.githubusercontent.com/u/178444?v=4","gravatar_id":"","url":"https://api.github.com/users/tomberek","html_url":"https://github.com/tomberek","followers_url":"https://api.github.com/users/tomberek/followers","following_url":"https://api.github.com/users/tomberek/following{/other_user}","gists_url":"https://api.github.com/users/tomberek/gists{/gist_id}","starred_url":"https://api.github.com/users/tomberek/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/tomberek/subscriptions","organizations_url":"https://api.github.com/users/tomberek/orgs","repos_url":"https://api.github.com/users/tomberek/repos","events_url":"https://api.github.com/users/tomberek/events{/privacy}","received_events_url":"https://api.github.com/users/tomberek/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2017-07-13T16:19:17Z","updated_at":"2017-08-23T23:44:46Z","closed_at":"2017-08-23T23:44:46Z","pull_request":{"url":"https://api.github.com/repos/EttusResearch/fpga/pulls/16","html_url":"https://github.com/EttusResearch/fpga/pull/16","diff_url":"https://github.com/EttusResearch/fpga/pull/16.diff","patch_url":"https://github.com/EttusResearch/fpga/pull/16.patch"},"body":"This resolves some warnings and sets a formal length for WINDOW_LEN. There may be a better way to define the parameter, but my Verilog is rusty."},"comment":{"url":"https://api.github.com/repos/EttusResearch/fpga/issues/comments/324492872","html_url":"https://github.com/EttusResearch/fpga/pull/16#issuecomment-324492872","issue_url":"https://api.github.com/repos/EttusResearch/fpga/issues/16","id":324492872,"user":{"login":"jpendlum","id":951880,"avatar_url":"https://avatars2.githubusercontent.com/u/951880?v=4","gravatar_id":"","url":"https://api.github.com/users/jpendlum","html_url":"https://github.com/jpendlum","followers_url":"https://api.github.com/users/jpendlum/followers","following_url":"https://api.github.com/users/jpendlum/following{/other_user}","gists_url":"https://api.github.com/users/jpendlum/gists{/gist_id}","starred_url":"https://api.github.com/users/jpendlum/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jpendlum/subscriptions","organizations_url":"https://api.github.com/users/jpendlum/orgs","repos_url":"https://api.github.com/users/jpendlum/repos","events_url":"https://api.github.com/users/jpendlum/events{/privacy}","received_events_url":"https://api.github.com/users/jpendlum/received_events","type":"User","site_admin":false},"created_at":"2017-08-23T23:44:46Z","updated_at":"2017-08-23T23:44:46Z","body":"Merged, will go public soon"}}
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