{"action":"created","issue":{"url":"https://api.github.com/repos/espressif/esp-idf/issues/353","repository_url":"https://api.github.com/repos/espressif/esp-idf","labels_url":"https://api.github.com/repos/espressif/esp-idf/issues/353/labels{/name}","comments_url":"https://api.github.com/repos/espressif/esp-idf/issues/353/comments","events_url":"https://api.github.com/repos/espressif/esp-idf/issues/353/events","html_url":"https://github.com/espressif/esp-idf/issues/353","id":208642466,"number":353,"title":"reboot on spi_flash_disable_cache / spi_flash_restore_cache","user":{"login":"ESP32DE","id":16070445,"avatar_url":"https://avatars.githubusercontent.com/u/16070445?v=3","gravatar_id":"","url":"https://api.github.com/users/ESP32DE","html_url":"https://github.com/ESP32DE","followers_url":"https://api.github.com/users/ESP32DE/followers","following_url":"https://api.github.com/users/ESP32DE/following{/other_user}","gists_url":"https://api.github.com/users/ESP32DE/gists{/gist_id}","starred_url":"https://api.github.com/users/ESP32DE/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ESP32DE/subscriptions","organizations_url":"https://api.github.com/users/ESP32DE/orgs","repos_url":"https://api.github.com/users/ESP32DE/repos","events_url":"https://api.github.com/users/ESP32DE/events{/privacy}","received_events_url":"https://api.github.com/users/ESP32DE/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":14,"created_at":"2017-02-18T13:40:52Z","updated_at":"2017-02-18T22:02:51Z","closed_at":null,"body":"```\r\nextern void spi_flash_disable_interrupts_caches_and_other_cpu();\r\nextern void spi_flash_enable_interrupts_caches_and_other_cpu();\r\n\r\nextern void spi_flash_disable_interrupts_caches_and_other_cpu_no_os();\r\nextern void spi_flash_enable_interrupts_caches_no_os();\r\n\r\n\r\n\r\n\r\n/**\r\n * The following two functions are replacements for Cache_Read_Disable and Cache_Read_Enable\r\n * function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to\r\n * Cache_Flush before Cache_Read_Enable, even if cached data was not modified.\r\n */\r\n\r\nstatic const uint32_t cache_mask  = DPORT_APP_CACHE_MASK_OPSDRAM | DPORT_APP_CACHE_MASK_DROM0 |\r\n        DPORT_APP_CACHE_MASK_DRAM1 | DPORT_APP_CACHE_MASK_IROM0 |\r\n        DPORT_APP_CACHE_MASK_IRAM1 | DPORT_APP_CACHE_MASK_IRAM0;\r\n\r\nstatic void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state)\r\n{\r\n    uint32_t ret = 0;\r\n    if (cpuid == 0) {\r\n        ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);\r\n    } else {\r\n        ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);\r\n    }\r\n    *saved_state = ret;\r\n}\r\n\r\nstatic void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)\r\n{\r\n    if (cpuid == 0) {\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);\r\n    } else {\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);\r\n    }\r\n}\r\n\r\n\r\n```\r\n\r\n\r\n\r\n\r\n```\r\nuint32_t cpuid = 1;\r\n    uint32_t* saved_state=0;\r\n\t\r\n\t\t\r\n\tprintf(\"try disable:..\\n\\r\");\r\n\tspi_flash_disable_cache(cpuid, (uint32_t *) saved_state);\r\n\t\r\n\tprintf(\"try restore:..\\n\\r\");\r\n\tspi_flash_restore_cache( cpuid, (uint32_t) saved_state);\r\n\t\r\n\tprintf(\"go in while..\\n\\r\");\r\n\twhile (-1) ;\r\n\r\n\r\n```\r\n\r\n\r\n\r\n\r\n\r\n\r\n> ets Jun  8 2016 00:22:57\r\n> \r\n> rst:0x1 (POWERON_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)\r\n> ets Jun  8 2016 00:22:57\r\n> \r\n> rst:0x10 (RTCWDT_RTC_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)\r\n> configsip: 0, SPIWP:0x00\r\n> clk_drv:0x0ets Jun  8 2016 00:22:57\r\n> \r\n> rst:0x10 (RTCWDT_RTC_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)\r\n> ets Jun  8 2016 00:22:57\r\n> \r\n> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)\r\n> configsip: 0, SPIWP:0x00\r\n> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00\r\n> mode:DIO, clock div:2\r\n> load:0x3fff0008,len:8\r\n> load:0x3fff0010,len:3388\r\n> ho 0 tail 12 room 4\r\n> load:0x40078000,len:7504\r\n> load:0x40080000,len:252\r\n> entry 0x40080034\r\n> I (47) boot: ESP-IDF v2.0-rc1-21-g30a557a 2nd stage bootloader\r\n> I (47) boot: compile time 13:34:58\r\n> I (47) boot: Enabling RNG early entropy source...\r\n> I (67) boot: SPI Speed      : 40MHz\r\n> I (80) boot: SPI Mode       : DIO\r\n> I (92) boot: SPI Flash Size : 4MB\r\n> I (105) boot: Partition Table:\r\n> I (116) boot: ## Label            Usage          Type ST Offset   Length\r\n> I (139) boot:  0 nvs              WiFi data        01 02 00009000 00006000\r\n> I (162) boot:  1 phy_init         RF data          01 01 0000f000 00001000\r\n> I (185) boot:  2 factory          factory app      00 00 00010000 00100000\r\n> I (209) boot: End of partition table\r\n> I (222) boot: Disabling RNG early entropy source...\r\n> I (239) boot: Loading app partition at offset 00010000\r\n> I (511) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512)\r\n> I (512) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x02298 (  8856) map\r\n> I (528) boot: segment 2: paddr=0x000222a8 vaddr=0x3ffb0000 size=0x01a98 (  6808) load\r\n> I (557) boot: segment 3: paddr=0x00023d48 vaddr=0x40080000 size=0x00400 (  1024) load\r\n> I (581) boot: segment 4: paddr=0x00024150 vaddr=0x40080400 size=0x07d08 ( 32008) load\r\n> I (622) boot: segment 5: paddr=0x0002be60 vaddr=0x400c0000 size=0x00000 (     0) load\r\n> I (633) boot: segment 6: paddr=0x0002be68 vaddr=0x00000000 size=0x041a0 ( 16800)\r\n> I (658) boot: segment 7: paddr=0x00030010 vaddr=0x400d0018 size=0x0c454 ( 50260) map\r\n> I (684) heap_alloc_caps: Initializing. RAM available for dynamic allocation:\r\n> I (707) heap_alloc_caps: At 3FFB20F8 len 0002DF08 (183 KiB): DRAM\r\n> I (728) heap_alloc_caps: At 3FFE8000 len 00018000 (96 KiB): D/IRAM\r\n> I (749) heap_alloc_caps: At 40088108 len 00017EF8 (95 KiB): IRAM\r\n> I (769) cpu_start: Pro cpu up.\r\n> I (781) cpu_start: Starting app cpu, entry point is 0x40080994\r\n> I (0) cpu_start: App cpu up.\r\n> I (812) cpu_start: Pro cpu start user code\r\n> I (872) cpu_start: Starting scheduler on PRO CPU.\r\n> I (877) example: Initializing SD card\r\n> try disable:..\r\n> GGuru Meditation Error of type IllegalInstruction occurred on core  1. Exception was unhandled.\r\n> Register dump:\r\n> PC      : 0x400d09f6  PS      : 0x00060d33  A0      : 0x800d0cdb  A1      : 0x3ffe7c90\r\n> A2      : 0x0000040e  A3      : 0x00000001  A4      : 0xffffffff  A5      : 0x00000003\r\n> A6      : 0x0000001f  A7      : 0x00000001  A8      : 0x800d0ae3  A9      : 0x00000000\r\n> A10     : 0x00000001  A11     : 0x00000001  A12     : 0x00000000  A13     : 0x3ffe7e30\r\n> A14     : 0x0000abab  A15     : 0x00000001  SAR     : 0x00000000  EXCCAUSE: 0x00000000\r\n> EXCVADDR: 0x00000000  LBEG    : 0x4000c2e0  LEND    : 0x4000c2f6  LCOUNT  : 0x00000000\r\n> \r\n> Backtrace: 0x400d09f6:0x3ffe7c90 0x400d0cdb:0x3ffe7cd0 0x400d0ebc:0x3ffe7d10 0x400d0934:0x3ffe7d40 0x4008097e:0x3ffe7d60 0x40080a0c:0x3ffe7d80 0x40007c34:0x3ffe7dc0 0x40000740:0x3ffe7e30\r\n> \r\n> Rebooting...\r\n> uets Jun  8 2016 00:22:57\r\n> \r\n> rst:0xc (SW_CPU_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)\r\n> configsip: 0, SPIWP:0x00\r\n> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00\r\n> mode:DIO, clock div:2\r\n> load:0x3fff0008,len:8\r\n> load:0x3fff0010,len:3388\r\n> ho 0 tail 12 room 4\r\n> load:0x40078000,len:7504\r\n> load:0x40080000,len:252\r\n> entry 0x40080034\r\n> ets Jun  8 2016 00:22:57\r\n> \r\n> rst:0x10 (RTCWDT_RTC_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)\r\n> configsip: 0, SPIWP:0x00\r\n> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00\r\n> mode:DIO, clock div:2\r\n> load:0x3fff0008,len:8\r\n> load:0x3fff0010,len:3388\r\n> ho 0 tail 12 room 4\r\n> load:0x40078000,len:7504\r\n> load:0x40080000,len:252\r\n> entry 0x40080034\r\n> I (47) boot: ESP-IDF v2.0-rc1-21-g30a557a 2nd stage bootloader\r\n> I (47) boot: compile time 13:34:58\r\n> I (47) boot: Enabling RNG early entropy source...\r\n> I (67) boot: SPI Speed      : 40MHz\r\n> I (80) boot: SPI Mode       : DIO\r\n> I (92) boot: SPI Flash Size : 4MB\r\n> I (105) boot: Partition Table:\r\n> I (116) boot: ## Label            Usage          Type ST Offset   Length\r\n> I (139) boot:  0 nvs              WiFi data        01 02 00009000 00006000\r\n> I (162) boot:  1 phy_init         RF data          01 01 0000f000 00001000\r\n> I (185) boot:  2 factory          factory app      00 00 00010000 00100000\r\n> I (209) boot: End of partition table\r\n> I (222) boot: Disabling RNG early entropy source...\r\n> I (239) boot: Loading app partition at offset 00010000\r\n> I (511) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512)\r\n> I (512) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x02298 (  8856) map\r\n> I (528) boot: segment 2: paddr=0x000222a8 vaddr=0x3ffb0000 size=0x01a98 (  6808) load\r\n> I (557) boot: segment 3: paddr=0x00023d48 vaddr=0x40080000 size=0x00400 (  1024) load\r\n> I (581) boot: segment 4: paddr=0x00024150 vaddr=0x40080400 size=0x07d08 ( 32008) load\r\n> I (622) boot: segment 5: paddr=0x0002be60 vaddr=0x400c0000 size=0x00000 (     0) load\r\n> I (633) boot: segment 6: paddr=0x0002be68 vaddr=0x00000000 size=0x041a0 ( 16800)\r\n> I (657) boot: segment 7: paddr=0x00030010 vaddr=0x400d0018 size=0x0c454 ( 50260) map\r\n> I (684) heap_alloc_caps: Initializing. RAM available for dynamic allocation:\r\n> I (707) heap_alloc_caps: At 3FFB20F8 len 0002DF08 (183 KiB): DRAM\r\n> I (728) heap_alloc_caps: At 3FFE8000 len 00018000 (96 KiB): D/IRAM\r\n> I (749) heap_alloc_caps: At 40088108 len 00017EF8 (95 KiB): IRAM\r\n> I (769) cpu_start: Pro cpu up.\r\n> I (781) cpu_start: Starting app cpu, entry point is 0x40080994\r\n> I (0) cpu_start: App cpu up.\r\n> I (812) cpu_start: Pro cpu start user code\r\n> I (872) cpu_start: Starting scheduler on PRO CPU.\r\n> I (877) example: Initializing SD card\r\n> try disable:..\r\n> GGuru Meditation Error of type IllegalInstruction occurred on core  1. Exception was unhandled.\r\n> Register dump:\r\n> PC      : 0x400d09f6  PS      : 0x00060d33  A0      : 0x800d0cdb  A1      : 0x3ffe7c90\r\n> A2      : 0x0000040e  A3      : 0x00000001  A4      : 0xffffffff  A5      : 0x00000003\r\n> A6      : 0x0000001f  A7      : 0x00000001  A8      : 0x800d0ae3  A9      : 0x00000000\r\n> A10     : 0x00000001  A11     : 0x00000001  A12     : 0x00000000  A13     : 0x3ffe7e30\r\n> A14     : 0x0000abab  A15     : 0x00000001  SAR     : 0x00000000  EXCCAUSE: 0x00000000\r\n> EXCVADDR: 0x00000000  LBEG    : 0x4000c2e0  LEND    : 0x4000c2f6  LCOUNT  : 0x00000000\r\n> \r\n> Backtrace: 0x400d09f6:0x3ffe7c90 0x400d0cdb:0x3ffe7cd0 0x400d0ebc:0x3ffe7d10 0x400d0934:0x3ffe7d40 0x4008097e:0x3ffe7d60 0x40080a0c:0x3ffe7d80 0x40007c34:0x3ffe7dc0 0x40000740:0x3ffe7e30\r\n> \r\n> Rebooting...\r\n> uets Jun  8 2016 00:22:57\r\n> \r\n> rst:0xc (SW_CPU_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)\r\n> configsip: 0, SPIWP:0x00\r\n> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00\r\n> mode:DIO, clock div:2\r\n> load:0x3fff0008,len:8\r\n> load:0x3fff0010,len:3388\r\n> ho 0 tail 12 room 4\r\n> load:0x40078000,len:7504\r\n> load:0x40080000,len:252\r\n> entry 0x40080034\r\n> I (47) boot: ESP-IDF v2.0-rc1-21-g30a557a 2nd stage bootloader\r\n> I (47) boot: compile time 13:34:58\r\n> I (47) boot: Enabling RNG early entropy source...\r\n> I (67) boot: SPI Speed      : 40MHz\r\n> I (80) boot: SPI Mode       : DIO\r\n> I (92) boot: SPI Flash Size : 4MB\r\n> I (105) boot: Partition Table:\r\n> I (116) boot: ## Label            Usage          Type ST Offset   Length\r\n> I (139) boot:  0 nvs              WiFi data        01 02 00009000 00006000\r\n> I (162) boot:  1 phy_init         RF data          01 01 0000f000 00001000\r\n> I (185) boot:  2 factory          factory app      00 00 00010000 00100000\r\n> I (209) boot: End of partition table\r\n> I (221) boot: Disabling RNG early entropy source...\r\n> I (239) boot: Loading app partition at offset 00010000\r\n> I (511) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512)\r\n> I (511) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x02298 (  8856) map\r\n> I (527) boot: segment 2: paddr=0x000222a8 vaddr=0x3ffb0000 size=0x01a98 (  6808) load\r\n> I (557) boot: segment 3: paddr=0x00023d48 vaddr=0x40080000 size=0x00400 (  1024) load\r\n> I (581) boot: segment 4: paddr=0x00024150 vaddr=0x40080400 size=0x07d08 ( 32008) load\r\n> I (621) boot: segment 5: paddr=0x0002be60 vaddr=0x400c0000 size=0x00000 (     0) load\r\n> I (632) boot: segment 6: paddr=0x0002be68 vaddr=0x00000000 size=0x041a0 ( 16800)\r\n> I (657) boot: segment 7: paddr=0x00030010 vaddr=0x400d0018 size=0x0c454 ( 50260) map\r\n> I (684) heap_alloc_caps: Initializing. RAM available for dynamic allocation:\r\n> I (707) heap_alloc_caps: At 3FFB20F8 len 0002DF08 (183 KiB): DRAM\r\n> I (728) heap_alloc_caps: At 3FFE8000 len 00018000 (96 KiB): D/IRAM\r\n> I (749) heap_alloc_caps: At 40088108 len 00017EF8 (95 KiB): IRAM\r\n> I (769) cpu_start: Pro cpu up.\r\n> I (781) cpu_start: Starting app cpu, entry point is 0x40080994\r\n> I (0) cpu_start: App cpu up.\r\n> I (812) cpu_start: Pro cpu start user code\r\n> I (871) cpu_start: Starting scheduler on PRO CPU.\r\n> I (877) example: Initializing SD card\r\n> try disable:..\r\n> GGuru Meditation Error of type IllegalInstruction occurred on core  1. Exception was unhandled.\r\n> Register dump:\r\n> PC      : 0x400d09f6  PS      : 0x00060d33  A0      : 0x800d0cdb  A1      : 0x3ffe7c90\r\n> A2      : 0x0000040e  A3      : 0x00000001  A4      : 0xffffffff  A5      : 0x00000003\r\n> A6      : 0x0000001f  A7      : 0x00000001  A8      : 0x800d0ae3  A9      : 0x00000000\r\n> A10     : 0x00000001  A11     : 0x00000001  A12     : 0x00000000  A13     : 0x3ffe7e30\r\n> A14     : 0x0000abab  A15     : 0x00000001  SAR     : 0x00000000  EXCCAUSE: 0x00000000\r\n> EXCVADDR: 0x00000000  LBEG    : 0x4000c2e0  LEND    : 0x4000c2f6  LCOUNT  : 0x00000000\r\n> \r\n> Backtrace: 0x400d09f6:0x3ffe7c90 0x400d0cdb:0x3ffe7cd0 0x400d0ebc:0x3ffe7d10 0x400d0934:0x3ffe7d40 0x4008097e:0x3ffe7d60 0x40080a0c:0x3ffe7d80 0x40007c34:0x3ffe7dc0 0x40000740:0x3ffe7e30\r\n> \r\n> Rebooting...\r\n> "},"comment":{"url":"https://api.github.com/repos/espressif/esp-idf/issues/comments/280878456","html_url":"https://github.com/espressif/esp-idf/issues/353#issuecomment-280878456","issue_url":"https://api.github.com/repos/espressif/esp-idf/issues/353","id":280878456,"user":{"login":"ESP32DE","id":16070445,"avatar_url":"https://avatars.githubusercontent.com/u/16070445?v=3","gravatar_id":"","url":"https://api.github.com/users/ESP32DE","html_url":"https://github.com/ESP32DE","followers_url":"https://api.github.com/users/ESP32DE/followers","following_url":"https://api.github.com/users/ESP32DE/following{/other_user}","gists_url":"https://api.github.com/users/ESP32DE/gists{/gist_id}","starred_url":"https://api.github.com/users/ESP32DE/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ESP32DE/subscriptions","organizations_url":"https://api.github.com/users/ESP32DE/orgs","repos_url":"https://api.github.com/users/ESP32DE/repos","events_url":"https://api.github.com/users/ESP32DE/events{/privacy}","received_events_url":"https://api.github.com/users/ESP32DE/received_events","type":"User","site_admin":false},"created_at":"2017-02-18T22:02:51Z","updated_at":"2017-02-18T22:02:51Z","body":"@igrr \r\n\r\n> In your last snippet you are disabling the cache and then calling printf. Printf can not work with cache disabled because it uses functions which are not in IRAM.\r\n\r\nuncleaned test code:\r\n=============\r\n\r\non bottom is the monitor output\r\n( scroll down)\r\n\r\n```\r\n#include <stdlib.h>\r\n#include <assert.h>\r\n#include <string.h>\r\n#include <stdio.h>\r\n\r\n#include <freertos/FreeRTOS.h>\r\n#include <freertos/task.h>\r\n#include <freertos/semphr.h>\r\n#include <rom/spi_flash.h>\r\n#include <rom/cache.h>\r\n#include <soc/soc.h>\r\n#include <soc/dport_reg.h>\r\n#include \"sdkconfig.h\"\r\n#include \"esp_ipc.h\"\r\n#include \"esp_attr.h\"\r\n#include \"esp_intr_alloc.h\"\r\n#include \"esp_spi_flash.h\"\r\n#include \"esp_log.h\"\r\n\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <sys/unistd.h>\r\n#include <sys/stat.h>\r\n#include \"esp_err.h\"\r\n#include \"esp_log.h\"\r\n#include \"esp_vfs_fat.h\"\r\n#include \"driver/sdmmc_host.h\"\r\n#include \"driver/sdmmc_defs.h\"\r\n#include \"sdmmc_cmd.h\"\r\n\r\n// #include <spi_flash/cache_utils.h>\r\n// #include \"spi_flash/cache_utils.h\"\r\n// #include \"cache_utils.h\"\r\n#include \"../cache_utils.h\"\r\n\r\n// #include \"driver/uart.h\"\r\n// #include \"freertos/queue.h\"\r\n// #include \"esp_log.h\"\r\n// #include \"soc/uart_struct.h\"\r\n\r\n\r\n\r\n\r\nstatic const char* TAG = \"example\";\r\n\r\nuint32_t cpuid = 1;\r\nuint32_t saved_state=0;\r\n\r\n\r\n// extern void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);\r\n// extern void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);\r\n\r\n// extern void spi_flash_disable_interrupts_caches_and_other_cpu();\r\n// extern void spi_flash_enable_interrupts_caches_and_other_cpu();\r\n\r\n// extern void spi_flash_disable_interrupts_caches_and_other_cpu_no_os();\r\n// extern void spi_flash_enable_interrupts_caches_no_os();\r\n\r\n\r\n\r\n\r\n/**\r\n * The following two functions are replacements for Cache_Read_Disable and Cache_Read_Enable\r\n * function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to\r\n * Cache_Flush before Cache_Read_Enable, even if cached data was not modified.\r\n */\r\n\r\nstatic const uint32_t cache_mask  = DPORT_APP_CACHE_MASK_OPSDRAM | DPORT_APP_CACHE_MASK_DROM0 |\r\n        DPORT_APP_CACHE_MASK_DRAM1 | DPORT_APP_CACHE_MASK_IROM0 |\r\n        DPORT_APP_CACHE_MASK_IRAM1 | DPORT_APP_CACHE_MASK_IRAM0;\r\n\r\nstatic void IRAM_ATTR spi_flash_disable_cache( uint32_t cpuid) // , uint32_t saved_state)\r\n{\r\n    uint32_t ret = 0;\r\n    if (cpuid == 0) {\r\n        ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);\r\n    } else {\r\n        ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);\r\n    }\r\n\t\r\n\tsaved_state = ret;\r\n\t\r\n    \r\n}\r\n\r\nstatic void IRAM_ATTR spi_flash_restore_cache( uint32_t cpuid) // , uint32_t saved_state)\r\n{\r\n    if (cpuid == 0) {\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);\r\n        SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);\r\n    } else {\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);\r\n        SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);\r\n    }\r\n}\r\n\r\n\r\nvoid testregister(void) {\r\n\t\r\n    // simple register test\r\n\t\r\n\tuint32_t testme = 0;\r\n\t\r\n\ttestme |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n\t\t\r\n\tprintf(\"ret cpu 0 : %p\\n\\r\", (uint32_t *) testme);\r\n\t\r\n\ttestme = 0;\r\n\t\r\n\ttestme |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);\r\n        while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {\r\n            ;\r\n        }\r\n\t\t\r\n\tprintf(\"ret cpu 1 : %p\\n\\r\", (uint32_t *) testme);\r\n\t\t\r\n}\r\n\r\n\r\nvoid IRAM_ATTR app_main(void)\r\n{\t\r\n    ESP_LOGI(TAG, \"..test app_main starts..\");\r\n\tvTaskDelay(1000 / portTICK_RATE_MS);\r\n\t\r\n\t// testregister();\r\n\t\r\n    printf(\"1) try disable cache\\n\\r\");\r\n\tfflush(stdout);\r\n\t\r\n\t// try disable cache cpuid 1\r\n\tspi_flash_disable_cache(1); // , (uint32_t) saved_state);\r\n\r\n\t// cache disabled - try printf here\r\n\tprintf(\"2) disabled - really cache_disabled?\\n\\r\");\r\n\tfflush(stdout);\r\n\t\r\n\tprintf(\"3) cache must be disabled..uah.. what happend ?\\n\\r\");\r\n\tfflush(stdout);\r\n    \r\n\t// cache disabled - try printf here\r\n\t// printf(\"testpoint 3\\n\\r\");\r\n\tprintf(\"4) try restore cache\\n\\r\");\r\n\tfflush(stdout);\r\n\r\n\t// try restore cache cpuid 1 \r\n\tspi_flash_restore_cache(1); // , (uint32_t) saved_state);\r\n\r\n\tprintf(\"5) cache restored\\n\\r\");\r\n\tfflush(stdout);\r\n\t\r\n\tprintf(\"u\");\r\n\tfflush(stdout);\r\n\tvTaskDelay(1000 / portTICK_RATE_MS);\r\n\t\r\n\tprintf(\"p\");\r\n\tfflush(stdout);\r\n\tvTaskDelay(1000 / portTICK_RATE_MS);\r\n\t\r\n\tprintf(\"s\");\r\n\tfflush(stdout);\r\n\tvTaskDelay(1000 / portTICK_RATE_MS);\r\n\t\r\n\tprintf(\"\\n\");\r\n\t// not need\r\n\t// fflush(stdout);\r\n\t\r\n\tprintf(\"closed\");\r\n\tvTaskDelay(3000 / portTICK_RATE_MS);\r\n\r\n\t// need because no newline \\n in printf's \"closed\" string\r\n\tfflush(stdout);\r\n}\r\n\r\n```\r\n\r\n![disable_cache_printf](https://cloud.githubusercontent.com/assets/16070445/23097178/df0f45c4-f62d-11e6-8cbc-c6a13e17e5fb.gif)\r\n\r\n\r\n\r\nbest wishes\r\nrudi ;-)"}}
{"actor":{"display_login":"ESP32DE"}}