<P> Instruction pipelining is a technique for implementing instruction - level parallelism within a single processor . Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps ( the eponymous `` pipeline '' ) , each performed by a different processor units , and occupying different units with parts of different instructions that are then processed in parallel . It allows faster CPU throughput than would otherwise be possible at a given clock rate , but may increase latency due to the added overhead of the pipelining process itself . </P>
in what way do instruction pipeline aid in parallel processing
attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps ( the eponymous `` pipeline '' ) , each performed by a different processor units occupying different units with parts of different instructions that are then processed in parallel