title: VHDL - Dynamic std_logic_vector size
body: <p>Is there a way in VHDL whereby I can declare a <code>std_logic_vector</code> such that the size of it keeps changing depending on the size of the input?</p>
  
  <p>What I would like to do is, input a <code>std_logic_vector</code> of 8 bits and then have a dynamic <code>std_logic_vector</code> signal that stores the input value. Then, the next time the input value is received again, I concatenate the value to the end of the dynamic signal and so on.</p>