title: Error adding std_logic_vectors
body: <p>I wanna have a simple module that adds two std_logic_vectors. However, when using the code
  below with the + operator it does not synthesize.     </p>
  
  <pre><code>library IEEE; 
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  
  entity add_module is
          port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
          );
  end add_module;
  
  architecture Behavior of add_module is
  
  begin
  
      pr_out &lt;= pr_in1 + pr_in2;
  
  end architecture Behavior;
  </code></pre>
  
  <p>The error message I get from XST</p>
  
  <p>Line 17. + can not have such operands in this context.</p>
  
  <p>Do I miss a library? If possible, I do not wanna convert the inputs into natural numbers.</p>
  
  <p>Many thanks</p>