title: D Flip Flop in VHDL
body: <p>I'm trying to implement a D Flip Flop in VHDL, using a D Latch I wrote.
  But there seems to be an error with the clock, and I can't figure out what that is.</p>
  
  <p>Here is the code for my D Latch.</p>
  
  <pre><code>Library ieee;
  Use ieee.std_logic_1164.all;
  
  entity d_latch is
    port (c,d : in std_logic;
          q,nq : out std_logic);
  end d_latch;
  
  architecture arch of d_latch is
  
  Signal qt, nqt: std_logic;
  
  begin  
  
    qt &lt;= (d nand c) nand nqt;
    nqt &lt;= ((not d) nand c) nand qt;
  
    q &lt;= qt;
    nq &lt;= nqt;
  
  end arch;
  </code></pre>
  
  <p>I tested it and it works, and here is the code for my d flip flop:</p>
  
  <pre><code>Library ieee;
  Use ieee.std_logic_1164.all;
  
  entity d_flipflop is
    port (d,clock : in std_logic;
          q,nq : out std_logic);
  end d_flipflop;
  
  architecture arch of d_flipflop is
  
  Component d_latch
  Port
  (
    d, clk: in std_logic;
    q, nq : out std_logic 
  );
  End Component ;
  
  Signal qt, nqt: std_logic;
  
  begin  
  
  dl1: d_latch port map (
    d =&gt; d,
    clk =&gt; not clock,
    q =&gt; qt
  );
  
  dl2: d_latch port map (
    d =&gt; qt,
    clk =&gt; clock,
    q =&gt; q,
    nq =&gt; nq
  );
  
  end arch;
  </code></pre>
  
  <p>and here is the error:</p>
  
  <pre><code>** Error: /home/devplayer/CSC343/Lab_2_Content/d_flipflop.vhd(25): (vcom-1436) Use of non globally static actual (prefix expression) of formal "clk" requires VHDL 2008.
  </code></pre>
  
  <p>Thank you</p>