title: Do locked instructions provide a barrier between weakly-ordered accesses?
body: <p>On x86, <code>lock</code>-prefixed instructions such as <code>lock cmpxchg</code> provide barrier semantics in addition to their atomic operation: for normal memory access on write-back memory regions, reads and writes are not re-ordered across <code>lock</code>-prefixed instructions, per section 8.2.2 of Volume 3 of the Intel SDM:</p>
  
  <blockquote>
    <p>Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.</p>
  </blockquote>
  
  <p>This section applies only to write-back memory types. In the same list, you find an exception where it notes that weakly ordered stores are not ordered:</p>
  
  <blockquote>
    <ul>
    <li>Reads are not reordered with other reads.</li>
    <li>Writes are not reordered
    with older reads. </li>
    <li>Writes to memory are not reordered with other
    writes, with the following exceptions: — 
    
    <blockquote>
      <p>streaming stores (writes) executed with the non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and — </p>
      
      <p>string operations (see Section 8.2.4.1).</p>
    </blockquote></li>
    </ul>
  </blockquote>
  
  <p>Note that there is no exception made for non-temporal instructions in any other items in the list, e.g., in the item referring to lock-prefixed instructions.</p>
  
  <p>In various other sections of the guide, it is mentioned that the <code>mfence</code> and/or <code>sfence</code> instructions can be used to order memory when weakly ordered (non-temporal) instructions are used. These sections generally don't mention <code>lock</code>-prefixed instruction as an alternative.</p>
  
  <p>All that leaves me uncertain: do <code>lock</code>-prefixed instructions provide the same full barrier that <code>mfence</code> provides between weakly ordered (non-temporal) instructions on WB memory? The same question applies again but to any type of access on WC memory.</p>