title: MMU page table descriptor size of indexes
body: <p>I am trying to setup a virtual address mapping with 2 levels of indirection for a Cortex-A v8 64bit in Baremetal. Page Table level 2 will contain Table descriptors and page Table level 3 will contains the block entries.</p>
  
  <p>By looking at the documentation for the 64KB pages:
  <a href="http://infocenter.arm.com/help/topic/com.arm.doc.den0024a/ch12s03.html#BABIIEFG" rel="nofollow noreferrer">http://infocenter.arm.com/help/topic/com.arm.doc.den0024a/ch12s03.html#BABIIEFG</a></p>
  
  <p>I don't understand how the size of the "Level 2 index" and "Level 3 index" are computed and if I need to follow the same way.
  In this example, table 2 has 8192 entries (so 13 bits are needed) and table 3 is addressed using 13 bits.
  Is is possible to change the size of the "Level 2 index"? How can I know the size of the index if I have 3 levels of indirection?</p>