title: range of modulus operator in verilog
body: <p>What is range of % operator in Verilog? In C I know if I write number%10 then output is between 0 and 9. But I tried in Verilog and result I am getting is between -9 and 9? Why is that? </p>
  
  <pre><code>enter code here
  module testbench;
  integer i;
  reg signed [15:0] a,b;
  initial
  begin
  for(i = 0; i &lt; 9; i = i + 1)
  begin
      a= $random%10;
      b= $random%20;  
      $display("A: %d and B : %d",a,b);
  end
  end
  endmodule
  </code></pre>