title: VHDL - AND operation between vector and bit
body: <p>i'm starting in VHDL, and I have a problem trying add a enable to a port. I have an output vector of 8 bits, and I want to put a value if the "Enable"bit input is '1'. Else, put a '0' in the vector.</p>
  
  <p>I can make:</p>
  
  <pre><code>out(0) &lt;= '0' AND Enable;
  out(1) &lt;= '0' AND Enable;
  out(2) &lt;= '1' AND Enable;
  out(3) &lt;= '0' AND Enable;
  out(4) &lt;= '1' AND Enable;
  ...
  out(7) &lt;= '0' AND Enable;
  </code></pre>
  
  <p>There are a easy way to make this? I'm thinking like: <code>out &lt;= "01010100" AND Enable;</code>
  but it doesn't work...</p>
  
  <p>I can use an "if", but i prefer use this way to understand how to do it.</p>