title: VHDL: [Place 30-574] Poor placement for routing between an IO pin and BUFG
body: <p>I am trying to design a stopwatch on Nexys4 DDR and get the following error:</p>
  <pre><code>[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
      &lt; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets en_IBUF] &gt;
  
      en_IBUF_inst (IBUF.O) is locked to IOB_X0Y82
       and en_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 
  </code></pre>
  <p>this is my code:</p>
  <pre><code>----------------------------------------------------------------------------------
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use ieee.numeric_std;
  
  
  entity cronometru is
       Port (clock: in std_logic;
              directie: in std_logic;
              SW: in std_logic_vector(14 downto 0);
              LED: inout std_logic_vector(14 downto 0);
              en: in std_logic;
              load: in std_logic;
              reset: in std_logic;
              AN: out std_logic_vector(7 downto 0);
              afis: out std_logic_vector(6 downto 0));
  end cronometru;
  
  architecture crono of cronometru is
  signal bcd: std_logic_vector(3 downto 0);
  signal bcd1: std_logic_vector(3 downto 0);
  signal bcd2: std_logic_vector(3 downto 0);
  signal bcd3: std_logic_vector(3 downto 0);
  signal bcd4: std_logic_vector(3 downto 0);
  signal bcd5: std_logic_vector(3 downto 0);
  signal refresh: std_logic_vector(2 downto 0);
  signal temp: std_logic:='1';
  signal copiat: std_logic_vector(14 downto 0);
  signal zecimal: integer range 0 to 32767;
  signal secunde: integer range 0 to 60;
  signal zeci_secunde: integer range 0 to 5;
  signal unitati_secunde: integer range 0 to 9;
  signal minute: integer range 0 to 60;
  signal zeci_minute: integer range 0 to 5;
  signal unitati_minute: integer range 0 to 9;
  signal unitati_ore: integer range 0 to 9;
  signal count: std_logic_vector(14 downto 0);
  signal enable: std_logic:='0';
  begin
  
  process(bcd) --here i display a digit
  begin
  case bcd is
  when &quot;0000&quot; =&gt; afis &lt;= &quot;0000001&quot;; -- &quot;0&quot;
  when &quot;0001&quot; =&gt; afis &lt;= &quot;1001111&quot;; -- &quot;1&quot;
  when &quot;0010&quot; =&gt; afis &lt;= &quot;0010010&quot;; -- &quot;2&quot;
  when &quot;0011&quot; =&gt; afis &lt;= &quot;0000110&quot;; -- &quot;3&quot;
  when &quot;0100&quot; =&gt; afis &lt;= &quot;1001100&quot;; -- &quot;4&quot;
  when &quot;0101&quot; =&gt; afis &lt;= &quot;0100100&quot;; -- &quot;5&quot;
  when &quot;0110&quot; =&gt; afis &lt;= &quot;0100000&quot;; -- &quot;6&quot;
  when &quot;0111&quot; =&gt; afis &lt;= &quot;0001111&quot;; -- &quot;7&quot;
  when &quot;1000&quot; =&gt; afis &lt;= &quot;0000000&quot;; -- &quot;8&quot;
  when &quot;1001&quot; =&gt; afis &lt;= &quot;0000100&quot;; -- &quot;9&quot;
  when others =&gt; afis &lt;= &quot;0110110&quot;;
  end case;
  end process;
  
  
  
  process(en) --  here i handle the stop signal 
  begin
  if (en'event and en='1') then
      enable&lt;=not enable;
  end if;
  end process;
  
  
  
  process(clock)--here i slow down the clock 
  variable cnt: integer:=0;
  begin
  if(clock'event and clock='1') then
      refresh&lt;=refresh+1;
      cnt:=cnt+1;
      if(cnt=50000001)then
          temp&lt;='0';
      end if;
      if(cnt=100000001) then
          temp&lt;='1';
          cnt:=1;
      end if;
  end if;
  end process;
  
  
  
  process(temp, reset, enable,directie,load)
  begin
  if reset='1' then
      count&lt;=(others=&gt;'0');
  elsif load='1' then 
      count&lt;=SW;
  elsif (temp='1' and temp'event) then
      if(directie='0' and enable='1') then
          count&lt;=count+1;
      elsif (directie='1' and enable ='1') then 
          count&lt;=count-1;
      else count&lt;=count;
      end if;
  end if;
  end process;
  LED&lt;=count;
  
  
  
  
  process(refresh)
  begin --here i find the value of each digit using the number of seconds
  copiat&lt;=LED;
  zecimal&lt;=conv_integer(unsigned(copiat));
  unitati_ore&lt;=zecimal/3600;
  minute&lt;=(zecimal mod 3600)/60;
  secunde&lt;=(zecimal mod 3600) mod 60;
  unitati_minute&lt;=minute mod 10;
  zeci_minute&lt;=minute/10;
  unitati_secunde&lt;=secunde mod 10;
  zeci_secunde&lt;=secunde/10;
  bcd1&lt;=conv_std_logic_vector(unitati_secunde,4);
  bcd2&lt;=conv_std_logic_vector(zeci_secunde,4);
  bcd3&lt;=conv_std_logic_vector(unitati_minute,4);
  bcd4&lt;=conv_std_logic_vector(zeci_minute,4);
  bcd5&lt;=conv_std_logic_vector(unitati_ore,4);
  case refresh is -- here i select what digit to be displayed
  when &quot;000&quot;=&gt; AN&lt;=&quot;11111110&quot;;
              bcd&lt;=bcd1;
  when &quot;001&quot;=&gt; AN&lt;=&quot;11111101&quot;;
              bcd&lt;=bcd2;
  when &quot;010&quot;=&gt; AN&lt;=&quot;11111011&quot;;
              bcd&lt;=bcd3;
  when &quot;011&quot;=&gt; AN&lt;=&quot;11110111&quot;;
               bcd&lt;=bcd4;
  when &quot;100&quot;=&gt; AN&lt;=&quot;11101111&quot;;
               bcd&lt;=bcd5;
  when &quot;101&quot;=&gt; AN&lt;=&quot;11111011&quot;;
               bcd&lt;=bcd3;
  when &quot;110&quot;=&gt; AN&lt;=&quot;11110111&quot;;
               bcd&lt;=bcd4;
  when &quot;111&quot;=&gt; AN&lt;=&quot;11101111&quot;;
               bcd&lt;=bcd5;                                                 
  when others =&gt; AN&lt;=&quot;11111111&quot;;
                  bcd&lt;=&quot;0000&quot;;
  end case;
  end process;
  end crono;
  </code></pre>
  <p>I can't understand why I'm facing this problem because in my previous implementations I used the clock in exactly same way. Is anybody able to help me?</p>
  <p>Here is the code from the constraints file that refer the clock:</p>
  <pre><code>set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clock }]; 
  #IO_L12P_T1_MRCC_35 Sch=clock
  create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clock}];
  </code></pre>