title: Cases throwing unexpected when
body: <p>I'm making a statemachine in VHDL. My case is throwing an unexpected when error</p>
  
  <pre><code>case state IS
              --state 1 A
              WHEN s0=&gt;
                  --Half step
                  if(FULL = '0' AND RIGHT = '1') then
                      state &lt;= s1;
                  else if (RIGHT = '0') then
                      state &lt;= s7;
                  end if;
  
                  --Full step
                  if (FULL = '1' AND RIGHT = '1') then
                      state &lt;= s2;
                  else if (RIGHT = '0') then
                      state &lt;= s6;    
                  end if;
  
              --State 2 A&amp;B
              WHEN s1=&gt;
                  if(RIGHT = '0') then
                      state &lt;= s0;
                  else if (RIGHT = '1') then
                      state &lt;= s2;
                  end if;
  </code></pre>
  
  <p>However, when running a syntax check with xilinx ISE I'm greeted with a</p>
  
  <pre><code>ERROR:HDLParsers:164 Line 72. parse error, unexpected WHEN, expecting END
  </code></pre>
  
  <p>This happens 8 times in total. What am I doing wrong?</p>