title: Confusing Makefile rules
body: <p>Just a little confused by Makefile working properly in the first example and absolutely not working in the second. </p>
  
  <p>Working:</p>
  
  <pre><code>CC=gcc
  CFLAGS=-Wall -Wextra -Werror
  FILES=$(addprefix src/, ft_putnbr ft_putchar main)
  OBJ=$(addsuffix .o, $(FILES))
  NAME=put
  
  $(NAME): $(OBJ)
      $(CC) -o $(NAME) $(OBJ)
  %.o: %.c
      gcc -c $^ -o $@ $(CFLAGS) -I includes/
  clean:
      rm -f $(OBJ)
  </code></pre>
  
  <p>Not working:</p>
  
  <pre><code>CC=gcc
  CFLAGS=-Wall -Wextra -Werror
  FILES=$(addprefix obj/, ft_putnbr ft_putchar main)
  OBJ=$(addsuffix .o, $(FILES))
  NAME=put
  
  $(NAME): $(OBJ)
      $(CC) -o $(NAME) $(OBJ)
  %.o: $(subst obj,src, %.c)
      gcc -c $^ -o $@ $(CFLAGS) -I includes/
  clean:
      rm -f $(OBJ)
  </code></pre>
  
  <p>The only difference being the FILES prefix set to obj/ because i wanted to separate obj files from source files and so i needed to use $(substitute) function to change the directory in one of the rules. 
  The second Makefile produces:</p>
  
  <pre><code>make: *** No rule to make target 'obj/ft_putnbr.o', needed by 'put'.  Stop.
  </code></pre>
  
  <p>Does anyone see my mistake here?</p>