title: concatenate inputs in verilog
body: <p>In my module I am taking two input 8-bits.</p>
  
  <pre><code>mymodule(input clk, input [7:0] AS_1,input [7:0] AS_2, output [7:0] AS)
  </code></pre>
  
  <p>Now I want to create a container that will keep both inputs, I mean I want to join them in a single one. I want to do something like that:</p>
  
  <pre><code>reg [15:0] JOIN = AS_1 and AS_2 ---&gt; all their bits should be arranged in a single container
  </code></pre>
  
  <p>But I don't know whether it should be a reg type or wire or something else, because I'll need to make other operations with that JOIN</p>
  
  <p>Any help, advise or suggestion would be highly appreciated!!!</p>