title: The strong-ness of x86 store instruction wrt. SC-DRF?
body: <p>I read about Herb's atomic&lt;&gt; Weapons talk and had a question about page 42:
  <a href="https://i.stack.imgur.com/4Q3bH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4Q3bH.png" alt="" /></a></p>
  <p>He mentioned that (50:00 in the <a href="https://www.youtube.com/watch?v=KeLBd2EJLOU" rel="nofollow noreferrer">video</a>):</p>
  <blockquote>
  <p>(x86) stores are much stronger than they need to be...</p>
  </blockquote>
  <p><strong>What I don't understand is</strong>: if the x86 &quot;S&quot; on the chart is a plain store, i.e. <code>mov</code>, I don't think it's stronger than SC-DRF because it's only a release store plus total store order (and that's why you need an <code>xchg</code> for a SC store). But if it means an SC store, i.e. <code>xchg</code>, it should fall on the &quot;fully SC&quot; bar because it's effectively a full barrier. <strong>How should I take this x86 &quot;S&quot;'s strong-ness on the chart?</strong></p>
  <p>(<a href="https://en.wikipedia.org/wiki/Race_condition#SC_for_DRF" rel="nofollow noreferrer">SC-DRF</a> is a guarantee of Sequentially Consistent execution for Data Race Free programs, as long as they don't use any atomics with orders weaker than <code>std::memory_order_seq_cst</code>.  ISO C++ and Java, and other languages, provide this.)</p>