title: Generating input numbers for a testbench of a 16x16bit multiplier
body: <p>I've been having some problems with creating a testbench for this code. It's supposed to be a 16x16bit multiplier. Basically, I want to create a testbench that will procedurally give A and B values so I can Assert the output of P.</p>
  <pre><code>    library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity multiplier_tb is
  --  Port ( );
  end multiplier_tb;
  
  architecture Behavioral of multiplier_tb is
  
      -- Component Declaration for the Unit Under Test (UUT)
      component multiplier is
          Port ( A, B : in STD_LOGIC_VECTOR (17 downto 0);
                 P : out STD_LOGIC_VECTOR (35 downto 0));
      end component multiplier;
  
      --Inputs
      signal A : std_logic_vector(17 downto 0) := (others =&gt; '0');
      signal B : std_logic_vector(17 downto 0) := (others =&gt; '0');
   
        --Outputs
      signal P : std_logic_vector(35 downto 0) := (others =&gt; '0');
      
      -- Clock definition
      signal clk : std_logic;
      constant clk_period : time := 10 ns;
  
  begin
      
      -- Instantiate the Unit Under Test (UUT)
      UUT: multiplier PORT MAP (A =&gt; A, B =&gt; B, P =&gt; P);
      
      stim_proc : process
      begin      
             for i in 0 to 2**18-1 loop
                 for k in 0 to 2**18-1 loop
     
                     wait for 0 ns;
     
                     A &lt;= conv_std_logic_vector(i, 18);
                     B &lt;= conv_std_logic_vector(k, 18);
             end loop;
         end loop;
         wait;
       end process;
      
  
  end Behavioral;
  </code></pre>