title: VHDL 3-bit u/d counter
body: <p>i have this vhdl code for a  3-bit up/down counter , but when i simulate it do not give any output result, what is wrong??</p>
  
  <pre><code>   library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;
  entity counter is
    Port ( rst,clk : in STD_LOGIC;
     up: in bit;
            z : out STD_LOGIC_vector( 2 downto 0 ));
  end counter;
  architecture Behavioral of Counter is
  signal zint:  STD_LOGIC_vector( 2 downto 0 ) ; 
  begin
  z&lt;= zint;
   process (clk)
  begin
  if (clk' event and clk='1') then 
  if (rst ='1') then 
  zint &lt;= "000" ;
  end if;
  if (zint &lt;= "111" )then zint &lt;= "000";
  elsif (up='1') then zint &lt;= zint+1;
  else zint &lt;= zint-1;
  end if;
  end if;
  end process;
  end Behavioral;
  </code></pre>