title: Verilog always vs assign
body: <p>Is it legal for a simulator to evaluate <code>clk_out1</code> in the next active Verilog scheduling window w.r.t <code>clk</code>? <code>clk_out2</code> seems to be updated in the same scheduling window as <code>clk</code>.</p>
  <pre><code>reg clk_out1;
  always @(*)
      clk_out1 = clk;
  
  assign clk_out2 = clk;
  </code></pre>
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