title: Defining an array in verilog down to a nonzero constant
body: <p>I have the following sub-module:</p>
  
  <pre><code>module test
  (
  input [LENGTH : 1] array;
  );
  
  ...
  
  endmodule
  </code></pre>
  
  <p>And I'm calling it from a top module as follows:</p>
  
  <pre><code>...
  wire [LENGTH-1 : 0] array_top;
  test test_i
  (
  .array (array_top);
  );
  ...
  </code></pre>
  
  <p>Assume LENGTH is the same in both modules.</p>
  
  <ol>
  <li>How will array_top map to array, given array_top goes down to zero but array goes to down 1?</li>
  <li>Why would anyone define an array down to 1 and not down to 0?</li>
  <li>What will happen to array[0]?</li>
  </ol>
  
  <p>Thanks,</p>