title: VHDL fsm error - near "when": (vcom-1576) expecting END
body: <p>I am trying to make a fsm in vhdl using modelsim but when i try and compile my code i have this errors</p>
  <blockquote>
  <p>** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(34): near &quot;when&quot;: (vcom-1576) expecting END.</p>
  <p>** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(60): near &quot;when&quot;: (vcom-1576) expecting END.</p>
  <p>** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(72): near &quot;else&quot;: (vcom-1576) expecting END.</p>
  </blockquote>
  <p>And this is my code</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity mult_fsm is
      port(ck,adx,m: in std_logic;
          adsh,sh,cm,mdone: out std_logic);
  end entity mult_fsm;
  
  architecture ideal of mult_fsm is
      type StateType is (S0, S1, S2, S3, S4);
      signal CurrentState, NextState: StateType;
  begin
      NS_CS: process( ck)
      begin
      if ck'event and ck='1' then
          case CurrentState is
              when S0=&gt;
              if (adx='0') then
                  NextState &lt;= S0;
              else
                  NextState &lt;= S1;
              end if;
  
              when S1=&gt;
                  NextState &lt;= S2;
  
              when S2=&gt;
              if (m='1') then
                  NextState&lt;=S3;
              else if (m='0') then
                  NextState&lt;=S2;
              end if;
              
              when S3=&gt;
                  NextState &lt;= S4;
  
              when S4=&gt;
                  NextState &lt;= S0;
  
          end case;
      end if;
      end process NS_CS;
  
      OL: process (CurrentState)
      begin
          case CurrentState is
              when S0=&gt;
              if (adx = '0') then
                  adsh&lt;='0';
                  sh&lt;='0';
                  cm&lt;='0';
                  mdone&lt;='0';
              else if (adx = '1') then
                  if (m='1') then
                      adsh&lt;='1';
                  else if (m='0') then
                      sh&lt;='1';
                  end if;
              end if;
              when S1=&gt;
              if (m='1') then
                  adsh&lt;='1';
              else if (m='0') then
                  sh&lt;='1';
              end if;
              when S2=&gt;
              if (m='0') then
                  adsh&lt;='0';
                  sh&lt;='0';
                  cm&lt;='0';
                  mdone&lt;='0';
              else if (m='1') then
                  adsh&lt;='1';
              end if;
              when S3=&gt;
              if (m='0') then
                  sh='1';
              else if (m='1') then
                  cm&lt;='1';
                  adsh&lt;='1';
              end if;
              when S4=&gt;
                  mdone&lt;='1';
          end case;
  
      end process OL;
  
  end architecture ideal;
  </code></pre>
  <p>I tried fixing the code myself but i just can't figure out what is the problem with it.</p>