title: Verilog Program Counter with branching
body: <p>I need to create a Verilog module which accepts the clock, a reset, the immediate value from the instruction word (least significant byte), and the zero output from the ALU as inputs and generates an 8-bit Program Counter (PC) for the output. The assignment says to note that in this architecture when we have a branch, the next PC value should be the current PC value plus the offset which is extracted from the branch instruction. The offset is represented in two’s complement, so the range of branch target is from PC - 128 to PC + 127. Note that the value of PC should not exceed 0xFF as we have a 256-deep instruction memory. You do not need to check for this condition in your hardware.</p>
  
  <p>Here's what I have so far but I know this is incomplete and I'm not sure what to do with the immediate or if I need to add something for the branch instruction. Any help/suggestions?</p>
  
  <pre><code>module pc(input clk,
      input rst,
      input [7:0] immediate,
      input alu_output,
      output [7:0] pc)
  
  reg [7:0] pc;
  
  always@(posedge clk)
      begin
          if(rst)
              begin
                  pc &lt;= 0;
              end
          else
              begin
                  pc &lt;= pc + 1;
              end             
      end
  endmodule
  </code></pre>