title: How to pass signal name through $value$plusargs in system verilog
body: <p>I am writing assertions in system verilog. This assertion check for a signal "lock" which is passed as an test argument through switch $value$plusargs as GPIO_SEL="test_bench.gpio"</p>
  
  <p>So my code is :</p>
  
  <pre><code>module ab 
  string abc;
  $value$plusargs("GPIO_SEL=%s" , abc);
  reg lock;
  always @* 
  begin
  lock = abc;
  end
  
  endmodule
  </code></pre>
  
  <p>The problem here is that signal lock is not getting value as test_bench.gpio. Is there any way i can pass this signal value from testplaus args</p>