title: Wrapping interfaces in array
body: <p>I am working with interfaces array used to bind parametrized modules.<br>
  My problem is that I cannot directly concatenate several simple interfaces into an array of interfaces.</p>
  
  <p>Here is a light version of the interface that I use:</p>
  
  <pre><code>interface channel ();
    wire req;
    wire ack;
    modport in (input req output ack);
    modport out(input ack output req);
  endinterface
  </code></pre>
  
  <p>What I want to do would be:</p>
  
  <pre><code>Channel array[2]();
  Channel elem0();
  Channel elem1();
  
  "assign" array = '{elem0,elem1};
  </code></pre>
  
  <p>I found a workaround using a module that assigns each wire independently:</p>
  
  <pre><code>module passthrough (Channel.in from, Channel.out to );
    assign to.req   = from.req;
    assign from.ack = to.ack;
  endmodule
  </code></pre>
  
  <p>Using it, I have to 'cast' each member element into each array member. Using the previous example:</p>
  
  <pre><code> passthrough pass0( .from(elem0), .to(array[0]));
   passthrough pass1( .from(elem1), .to(array[1]));
  </code></pre>
  
  <p>I do not like it though as the primary idea about using parametrized modules was to make my RTL clearer, shorter and maintainable. </p>
  
  <p>I naturally put the instantiation of this <code>passthrough</code>module in a macro but still, I am not satisfied.</p>
  
  <p>I then stumbled on tasks embeded in interfaces. Although I am not quite familiar with tasks in (S)Verilog so I do not think that my idea would work. Here is however what I tried:</p>
  
  <pre><code>interface channel ();
    reg req;
    reg ack;
    modport in (input req output ack);
    modport out(input ack output req);
  
    task wrap_from (Channel.in I);
      always@* begin
        req = I.req;
        I.ack = ack;
      end
    endtask
  endinterface
  </code></pre>
  
  <p>The advantage of this method would be that I would not need to create a module each time I need to connect 2 channels. The code line would also be shorter.</p>
  
  <p>Unfortunately, my compiler(ncsim) does not recognize <code>channel</code> as an interface inside the its own declaration(I guess it needs the <code>endinterface</code> keyword to consider it in the namespace).</p>
  
  <p>I would be extremely grateful if anyone has a cleaner than solution than me for this problem. </p>
  
  <p>One last thing, everything needs to be synthetisable.</p>