title: Debugging Iteration Limit error in VHDL Modelsim
body: <p>I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: </p>
  
  <blockquote>
    <p>Error: (vsim-3601) Iteration limit reached at time 400 ps.</p>
  </blockquote>
  
  <p>I'm not sure what it means, but I've looked through much of my source code for errors to no success. Can anyone guess what the problem might be?</p>