title: VHDL: error while working with two dimensional array
body: <p>I have a two dimensional array, I call it Memory. </p>
  
  <pre><code>type mem is array (0 to 79) of integer range 0 to 255;      -- 80 times by 8 bit 
  type dataArray is array (0 to 7) of mem;                    -- 8 arrays of 640bit 
  variable Memory: dataArray;                                 -- Here they are
  </code></pre>
  
  <p>And I have a SLV, answering on some requests, and is represented by integers in that array</p>
  
  <pre><code>inAnsw  :   in STD_LOGIC_VECTOR(7 downto 0);        -- the incoming bus
  inVALID :   in STD_LOGIC                            -- the signal
  </code></pre>
  
  <p>on some incoming signal, that indicates that I have 14 new bytes of data, i have to collect the incoming 12 bytes of that data in my array in a special order. The code looks like this:</p>
  
  <pre><code>    if falling_edge(inVALID) then   -- 14 signals will come         
          bytenum := bytenum + 1;     -- count them to know we 
          if (bytenum = 14) then      -- start every new session with
              bytenum := 0;           -- a zero position
              answmem := answmem + 1; -- increment the array position for  
              if (answmem = 8) then answmem := 0; end if;     -- the next answer
          end if;
  
  -- And here comes the huge problem. i am working with this 
  -- huge CASE, that puts a significant answer to the needed place 
  -- of my array. it works fine, but it takes more than 1500 logic 
  -- cells of my FPGA. 
  
          case bytenum is
              when 0 =&gt; Memory(answmem)(0) := TO_INTEGER(unsigned(inAnsw));               
              when 1 =&gt; Memory(answmem)(7) := TO_INTEGER(unsigned(inAnsw));
              when 2 =&gt; Memory(answmem)(9) := TO_INTEGER(unsigned(inAnsw));
              when 3 =&gt; Memory(answmem)(10) := TO_INTEGER(unsigned(inAnsw));
              when 4 =&gt; Memory(answmem)(17) := TO_INTEGER(unsigned(inAnsw));
              when 5 =&gt; Memory(answmem)(19) := TO_INTEGER(unsigned(inAnsw));
              when 6 =&gt; Memory(answmem)(20) := TO_INTEGER(unsigned(inAnsw));
              when 7 =&gt; Memory(answmem)(27) := TO_INTEGER(unsigned(inAnsw));
              when 8 =&gt; Memory(answmem)(30) := TO_INTEGER(unsigned(inAnsw));
              when 9 =&gt; Memory(answmem)(37) := TO_INTEGER(unsigned(inAnsw));
              when 10 =&gt; Memory(answmem)(40) := TO_INTEGER(unsigned(inAnsw));
              when 11 =&gt; Memory(answmem)(47) := TO_INTEGER(unsigned(inAnsw));
              when others =&gt; Memory(answmem)(67) := TO_INTEGER(unsigned(inAnsw));
          end case;
      end if; 
  </code></pre>
  
  <p>So if i try to replace the code that writes data with some other constructs, like the following or any other, using IF/ELSIF statements</p>
  
  <pre><code>if (bytenum &lt;12) then
      Memory (answmem)(bytenum+whatever) := TO_INTEGER(UNSIGNED(inAnsw));
  end if;
  </code></pre>
  
  <p>The symbol compilation works fine, and it takes about 100-200 logic cells, but when i start to compile a full project, I have a huge list of compilation errors</p>
  
  <pre><code>Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][0]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][0]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][1]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][1]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][2]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][2]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][3]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][3]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][4]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][4]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][5]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][5]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][6]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][6]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(217): can't infer register for "Memory[7][25][7]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(199): can't infer register for "Memory[7][25][7]" because its behavior does not match any supported register model
  Error (10821): HDL error at MyModule.vhd(203): can't infer register for "Memory[7][18][0]" because its behavior does not match any supported register model
  Error (10820): Netlist error at MyModule.vhd(199): can't infer register for Memory[7][18][0] because its behavior depends on the edges of multiple distinct clocks
  Error (10821): HDL error at MyModule.vhd(203): can't infer register for "Memory[7][18][1]" because its behavior does not match any supported register model
  </code></pre>
  
  <p>and the list is always the same, a couple of errors about behavior, and one about distinct clock edges</p>