title: Makefile automatic variables
body: <p>I'm working on a library of (more or less random ) c functions that I use in projects. The previous incarnation of it had every .c, .o file listed and manually compiled in target:</p>
  
  <pre><code>$(CC) $(SRCDIR)/somefoo.c $(CFLAGS) ... -c -o $(OBJDIR)/somefoo.o
  </code></pre>
  
  <p>This became tiresome, inaccurate and a pain, and I wanted to create a friendlier, better Makefile I could use for any project. After googling, reading( O'Reily's "Managing Projects with GNU Make ) and thinking I came up with:</p>
  
  <pre><code>BIN = /usr/bin
  
  SH  = $(BIN)/bash
  CC  = $(BIN)/cc
  AR  = $(BIN)/ar
  RL  = $(BIN)/ranlib
  RM  = $(BIN)/rm
  CP  = $(BIN)/cp
  RL  = $(BIN)/ranlib
  TC  = $(BIN)/touch
  MK  = $(BIN)/make
  FND = $(BIN)/find
  TAR = $(BIN)/tar
  RM  = $(BIN)/rm
  
  CFLAGS  = -Wall -Wextra -Wpedanitc -pedanitc-errors\
            -w -Waddress -Walloc-zero -Walloca -Warray-bounds\
            -Wno-deprecated -Wno-div-by-zero -Werror -Wfatal-errors\
            -Wduplicated-cond -Wduplicated-branches -Wlogical-op -Wdouble-promotion\
            -Wrestrict -Wnull-dereference -Wjump-misses-init -Wshadow\
            -Wformat=2 -Wformat -Wformat-security -pedantic --std=c99 --march=native
  DEBUG   = -g -ggdb -gstabs
  OPTIM   = -faggressive-loop-optimizations -fassociative-math -O3
  LIBS    = -lm -lcommonC #add more here
  INC     = -I/usr/include -I/usr/local/include -I$(INCDIR)
  LIBPATH = -L/usr/lib -L/usr/lib64 -L/usr/local/lib -L/usr/local/lib64 -L$(LIBDIR)
  MKFLAG  = -f
  
  PACK = $(TAR) -cvs
  EXTRACT = $(TAR) -xf
  
  PREFIX = /path/to/project #root directory of the project
  BINDIR = $(PREFIX)/bin #stores Makefile, shell scripts, README, LICENSE, data files...
  INCIDR = $(PREFIX)/include #holds .h files for the project
  SRCDIR = $(PREFIX)/src #holds source files
  OBJDIR = $(PREFIX)/obj #holds generated object files
  LIBDIR = $(PREFIX)/lib #holds generated or included .a files
  EXEDIR = $(PREFIX)/exe #generated executable(s)
  DESTDIR ?= #where the tar file will be unpacked, user defined.
  
  SRC = $(wildcard $(SRCDIR)/*.c) #all .c source files
  OBJ = $(patsubst %.c,%.o,$(wildcard *.c)) #.o files
  LIB ?= $(wildcard $(LIBDIR)/*.a) #the .a
  EXE = $(EXEDIR)/project #generated executable
  MKE = $(BINDIR)/Makefile #Makefile, used for cleaning before packing the project
  TARF ?= #tar file for project.tar, user defined
  
  .PHONY: obj exe update test clean pack install
  
  # up to $(EXE) updated thanks to "Renaud Pacalet"
  obj: $(OBJ)
  exe: $(EXE)
  
  $(OBJ): %.o: %.c
    $(CC) $&lt; $(CFLAGS) $(LIB) $(INC) $(LIBPATH) $(LIBS) $(OPTIM) -c -o $@
  
  $(EXE): $(OBJ)
     $(CC) $^ $(CFLAGS) $(LIB) $(INC) $(LIBPATH) $(LIBS) $(OPTIM) -o $@
  
  update: $(SRC)
      $(TC) $(SRC)
  
  clean:
      $(RM) $(OBJ) $(EXE) $(LIB)
  
  pack:
      $(MK) $(MKFLAG) $(MKE) clean &amp;&amp; $(PACK) $(PREFIX) $(TARF)
  
  install:
      cd $(DESTDIR) &amp;&amp; $(TAR) $(EXTRACT) $(TARF)
  </code></pre>
  
  <p>My question is with the declaration of SRC, OBJ, and the target to compile .c -> .o The SRC = ... works fine, but for some reason the corresponding obj file is not being generated? Thank you for any and all input.</p>
  
  <p>Update: Thanks to Renaud Pacalet, I have the OBJ/SRC variables figured out. I have been receiving an error:</p>
  
  <pre><code>make: Nothing to be done for 'obj'
  </code></pre>
  
  <p>Which usually means that the targets are up to date. It was brought to my attention that there is a lack of detail concerning my organization, so I added comments describing what each variable references. I have used this organization scheme before for most of my projects, and I have not had an issue with this until now.</p>
  
  <p>Thank you for any and all input.</p>
  
  <p>--Jordan.</p>
  
  <p>-- Jordan.</p>