title: STM32 USB OTG: how does one properly flush the Tx FIFO?
body: <p>STM32 manual for the F4xx series chips says that the application writes <code>TXFFLSH</code> bit in the <code>OTG_FS_GRSTCTL</code> register to flush the TxFIFO. As a note it mentions that <em>...application must write this bit only after checking that the core is neither writing to the
  TxFIFO nor reading from the TxFIFO</em>. As a means to do that, it suggests making sure that the NAK Effective Interrupt is set (I presume this means the <code>GINAKEFF</code> bit in <code>OTG_FS_GINTSTS</code> register) to ensure the core is not reading the FIFO, and checking that <code>AHBIDL</code> (AHB idle) bit in <code>OTG_FS_GRSTCTL</code> is set to guarantee that nothing is being written in the FIFO. The (awful) USB OTG library supplied by STM itself ignores both of these checks, while the free <code>libopencm3</code> library only checks the AHB idle bit. My questions are the following:</p>
  
  <ol>
  <li><p>The manual does not suggest disabling the USB OTG core before performing the above checks and writing the <code>TXFFLSH</code> bit. Does this not leave open the possibility that the core might start using the FIFO between the time the checks are performed and the writing of the <code>TXFFLSH</code>?</p></li>
  <li><p>The 'NAK Effective' bit only guarantees that no data is read from the TxFIFO for non-periodic endpoints. Would this not still make it possible for the core to utilize the FIFO for isochronous endpoints unless the core is disabled? </p></li>
  </ol>
  
  <p>I know these are 'nitpicking' type questions but the project I am working on is supposed to result in a very reliable piece of hardware, where the customer cannot afford checking the device for years so these subtleties matter (yes, we have a watchdog enabled, etc. but we need the core to work without resets most of the time).</p>