title: Verilog: Design counter using adder
body: <p>The following is one simple 4 bit up counter verilog code I made using a 4 bit adder verilog code ( a working file , tested). I happens that when I include the adder instantiation the clock stops working and hence entire code stops working. Any suggestions of what possibly went wrong????</p>
  
  <pre><code>module four_bit_counter(
  output reg [3:0] a
  );
   reg clock ;
   reg [3:0] temp;
   initial
   begin
      a = 4'b0000;
      clock =0 ;
      temp = 4'b0000;   // Remove this
   end
  
   four_bit_adder add(.a(temp), .b(4'b0001), .s(a));   //  four_bit_adder add(.a(a), .b(4'b0001), .s(temp));
  
   always  begin 
      #10 clock = ~clock;
   end
  
   always @(posedge clock) 
      begin 
          assign temp = a;  // a&lt;=temp;
      end
  
  endmodule
  </code></pre>
  
  <p>// 4 bit adder code:</p>
  
  <p>module four_bit_adder( </p>
  
  <pre><code> input  [3:0] a, 
   input  [3:0] b,
  output reg [3:0] s  // Type wire
  ); 
   wire [3:0] sum;   
   wire [3:0] c ; 
      full_adder f1( .a(a[0]) , .b(b[0]), .cin(1'b0), .s(sum[0]), .c(c[0]) );
      full_adder f2( .a(a[1]) , .b(b[1]), .cin(c[0]), .s(sum[1]), .c(c[1]) );
      full_adder f3( .a(a[2]) , .b(b[2]), .cin(c[1]), .s(sum[2]), .c(c[2]) ); 
      full_adder f4( .a(a[3]) , .b(b[3]), .cin(c[2]), .s(sum[3]), .c(c[3]) );
  
      always begin 
          assign s = sum;
      end 
  </code></pre>
  
  <p>endmodule</p>