title: Verilog blocking/nonblocking assignment in clk generator with self triggered
body: <p>Why the following code is not self-triggered? </p>
  
  <pre><code>module osc1 (clk);
  output clk;
  reg clk;
  initial #10 clk = 0;
  always @(clk) #10 clk = ~clk;
  
  always
  begin
  $monitor("%0d clk=%0d\n",$time,clk);
  #100 $finish;
  end
  endmodule
  </code></pre>
  
  <p>output: </p>
  
  <pre><code># 0 clk=x
  # 10 clk=0
  # 20 clk=1
  </code></pre>
  
  <p>when used non-blocking assignment it works normally<br/>
  i.e., <code>always @(clk) #10 clk &lt;= ~clk;</code></p>
  
  <p>output:</p>
  
  <pre><code># 0 clk=x 
  # 10 clk=0 
  # 20 clk=1
  # 30 clk=0
  # 40 clk=1
  # 50 clk=0 
  # 60 clk=1 
  # 70 clk=0
  # 80 clk=1
  # 90 clk=0
  </code></pre>
  
  <p>thanks in advance.</p>