title: Variable shift register in verilog
body: <p>I want to design a variable shift  register to shift to the right as follows:</p>
  <pre><code>module sr(N,int,out);
  
    input [2:0] N;
    input [7:0] in;
    output [7:0] out;
  
    assign out={N'b0,input[7,N]}
  
  endmodule
  </code></pre>
  <p>But unfortunately, Verilog doesn't allow this kind of writing. N should be constant.
  Any idea on how to get shift iterations from input?</p>