title: Unable to compare part of a std_logic_vector to a constant
body: <p>So in VHDL, I have a signal that's a std_logic_vector called A (let's say it's 32 bits). I want to look at bits 31...28 of A, check if it's 0001, and then do something if it is. So I have an if statement set up like this:</p>
  
  <pre><code>if (A(3 downto 0) = "0001") then:
      --do something
  </code></pre>
  
  <p>The problem I'm having is that I'm getting errors related it, but I'm not being told exactly what the error is:</p>
  
  <pre><code>ERROR:HDLCompiler:806 - "/home/csmajs/jchio001/Desktop/bcd_alu/bcd_alu.vhd" Line 104: Syntax error near "when".
  ERROR:HDLCompiler:806 - "/home/csmajs/jchio001/Desktop/bcd_alu/bcd_alu.vhd" Line 108: Syntax error near "when".
  ERROR:HDLCompiler:806 - "/home/csmajs/jchio001/Desktop/bcd_alu/bcd_alu.vhd" Line 110: Syntax error near "case".
  </code></pre>
  
  <p>(I have the if statement in a case statement)
  As you can see, I'm being told the there's an error with the code around it, rather than being told that there's an error with this if statement. If I remove the if statement from my code, everything's fine, so I know that it's the if statement that's invalid. So what's wrong with this if statement?</p>
  
  <p>Full code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  use IEEE.NUMERIC_STD.ALL;
  
  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity my_bcd_alu is
      Port ( A : in  STD_LOGIC_VECTOR(31 downto 0);
             B : in  STD_LOGIC_VECTOR(31 downto 0);
             Opcode : in  STD_LOGIC_VECTOR(3 downto 0);
             Result : out  STD_LOGIC_VECTOR(35 downto 0);
             Carry_out : out  STD_LOGIC;
             Overflow : out  STD_LOGIC;
             Zero : out  STD_LOGIC);
  end my_bcd_alu;
  
  architecture Behavioral of my_bcd_alu is
  signal temp: std_logic_vector(35 downto 0);
  signal sig_A: std_logic_vector(31 downto 0);
  signal sig_B: std_logic_vector(31 downto 0);
  Variable tempA: INTEGER;
  Variable tempB: INTEGER;
  Variable decA: INTEGER;
  Variable decB: INTEGER;
  begin
  process(A, B, Opcode, temp, sig_A, sig_B)
  begin
      decA := 0;
      decB := 0;
      tempA := TO_INTEGER(unsigned(A(3 downto 0)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(7 downto 4)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(11 downto 8)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(15 downto 12)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(19 downto 16)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(23 downto 20)));
      decA := decA + tempA;
      tempA := TO_INTEGER(unsigned(A(27 downto 24)));
      decA := decA + tempA;           
  
      tempB := TO_INTEGER(unsigned(B(3 downto 0)));
      decB := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(7 downto 4)));
      decB := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(11 downto 8)));
      decA := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(15 downto 12)));
      decB := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(19 downto 16)));
      decB := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(23 downto 20)));
      decB := decB + tempB;
      tempB := TO_INTEGER(unsigned(B(27 downto 24)));
      decB := decB + tempB;           
      case Opcode is
          when "1000" =&gt;          
              tempA := TO_INTEGER(unsigned(A(31 downto 28)));
              decA := decA + tempA;
              tempB := TO_INTEGER(unsigned(B(31 downto 28)));
              decB := decB + tempB;
              temp &lt;= std_logic_vector(TO_UNSIGNED(decA + decB, 35));
          when "1001" =&gt;
              tempA := TO_INTEGER(unsigned(A(31 downto 28)));
              decA := decA + tempA;
              tempB := TO_INTEGER(unsigned(B(31 downto 28)));
              decB := decB + tempB;                   
              temp &lt;= std_logic_vector(TO_UNSIGNED(decA - decB, 35));
          when "1100" =&gt;
              sig_A &lt;= std_logic_vector(TO_SIGNED(tempA, 32));            
              if (A(31 downto 28) = "0001") then --ERRORS HERE
                  sig_A &lt;= std_logic_vector(TO_SIGNED(tempA, 32));            
                  sig_A &lt;= NOT(sig_A);
              end if;
          when "1101" =&gt;          
              if (A(31 downto 28) = "0001") then
                  sig_A &lt;= std_logic_vector(TO_SIGNED(tempA - 1, 32));            
                  sig_A &lt;= NOT(sig_A);
              end if;
          when others =&gt;
              temp &lt;= "0000"&amp;A;
      end case;
  
  end process;
  end Behavioral;
  </code></pre>
  
  <p>EDIT: Adding end if removed the errors, but now I get:</p>
  
  <pre><code>Line 48: Variable outside of subprogram or process must be 'shared'
  </code></pre>