title: Coverpoint bins to cover all the bits
body: <p>I'm just a beginner in SystemVerilog and now I'm reading about coverage. So I have a doubt regarding this. How can I write the coverpoint bins to cover all the bits of a signal?</p>
  
  <pre><code>    interface allSignals;
          logic [31:0] addr;
          logic [15:0] len;
          bit trigger;
  
      covegroup signalOne@trigger;
  
          coverpoint addr; //This generates bins automatically(64 bins by 
                            default) with each bin containing 2^32/64 values
  
          coverpoint addr[0]; //each coverpoint covers 2 bins and 50% coverage 
          coverpoint addr[1]; //is shown even if the value is not covered in 
                 ...          //that bin
                 ...
          coverpoint addr[31];
  
          coverpoint addr{
              bins a0[] = {[0:5000]};     //should write 2^32 values which is 
              bins a1[] = {[5001:10000]}; //very complex
                 ...
                 ...
              }
  
          ad: coverpoint addr{
                  bins a[100] = ad; //creates 100 bins with 2^32/100 values in 
                  }                  //each bin
  
      endgroup
  
          signalOne cvr1 = new;
  
      endinterface
  </code></pre>
  
  <p>How can I write a coverpoint which covers all the 32-bits of "addr" signal. Is there any other better way to do this.</p>