title: Using variables from one entity into another in VHDL
body: <p>I have a little question related to my VHDL code. I have to create a simulation for 1 bit of ALU. I created a D flip-flop and a Full Adder, and now I have to connect them with some simple logical gates. How can I do to use variables from this 2 entities to do this?</p>
  
  <p>My code is:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  
  ENTITY D_flipflop IS PORT (
          D, Clock: IN STD_LOGIC;
          Q: OUT STD_LOGIC);
  END D_flipflop;
  ARCHITECTURE Behavior OF D_flipflop IS
      BEGIN
          PROCESS(Clock)
          BEGIN
          IF Clock'EVENT AND Clock = '0' THEN
              Q&lt;= D;
          END IF;
      END PROCESS;
  END Behavior;
  
  ENTITY fa IS PORT (
          Ci, Xi, Yi: IN STD_LOGIC ;
          Ci1, Si: OUT STD_LOGIC) ;
  END fa;
  
  ARCHITECTURE Dataflow OF fa IS
      BEGIN
          Ci1 &lt;= (Xi AND Yi) OR (Ci AND (Xi XOR Yi));
          Si &lt;= Xi XOR Yi XOR Ci;
  End Dataflow ;
  </code></pre>