title: How does " virtual" keyword work in systemverilog?
body: <p>I'm trying to understand 'virtual' keyword along with function.</p>
  
  <p>I've got some experiment as the below, </p>
  
  <pre><code>  class A ; 
           function void disp (); 
            $display(" Non-Virtual from A "); 
          endfunction
          virtual function void vdisp (); 
            $display(" Virtual from A "); 
          endfunction
        endclass 
  
        class EA extends A ;
            function void disp (); 
            $display(" Non-Virtual from EA "); 
          endfunction
           virtual function void vdisp (); 
            $display(" Virtual from EA "); 
          endfunction
        endclass 
  
      module main ; 
  
        function void disp( A a);
          a.disp();
          a.vdisp();
        endfunction
  
          A my_a; 
          EA my_ea;
  
  
        initial 
        begin 
          my_a = new(); 
          my_ea = new(); 
  
          disp(my_a); 
          disp(my_ea); 
  
        end 
      endmodule
  </code></pre>
  
  <p>and I've got the below message from code,</p>
  
  <pre><code>Non-Virtual from A 
   Virtual from A 
   Non-Virtual from A 
   Virtual from EA 
  </code></pre>
  
  <p>But my expectation is that should be like this,</p>
  
  <pre><code> Non-Virtual from A 
   Virtual from A 
   Non-Virtual from EA 
   Virtual from EA 
  </code></pre>
  
  <p>What does " vitual" keyword  work in systemverilog?</p>
  
  <p>Would you please explain why do I get this result? and how to resolve this problem?</p>