title: Atomic 16 byte read on x64 CPUs
body: <p>I need to read/write 16 bytes atomically. I do the writing only using cmpxchg16, which is available on all x64 processors except I think for one obscure AMD one.</p>
  
  <p>Now the question is for aligned 16 byte values, only ever modified using cmpxchg16 (which acts like a full memory barrier) is it ever possible to read a 16 byte location that's half old data and half new data?</p>
  
  <p>As long as I read with a SSE instruction (so the thread cannot be interrupted in the middle of the read) I think that it's impossible (even in multiprocessor numa systems) for the read to see inconsistent data. I think it must be atomic.</p>
  
  <p>I am making the assumption that when cmpxchg16 is executed, it modifies the 16 bytes atomically, not by writing two 8 byte blocks with the potential for other threads to do a read in between (honestly I don't see how it could work if it wasn't atomic.)</p>
  
  <p>Am I right? If I'm wrong, is there a way to do an atomic 16 byte read without resorting to locking? </p>
  
  <p>Note: There are a <a href="https://stackoverflow.com/questions/7646018/sse-instructions-single-memory-access">couple similar questions here</a> but they don't deal with the case where the writes are done only with cmpxchg16, so I feel this is a seperate, unanswered question.</p>
  
  <p><strong>Edit:</strong> Actually I think my reasoning was faulty. An SSE load instruction may be executed as two 64bit reads, and it may be possible for the cmpxchg16 to be executed in between the two reads by another processor.</p>