title: How to force make to always rebuild a file
body: <p>I have a version.c file in my project that contains current revision of the project and some other stuff that is passed as a definition (-D compiler option) from makefile.</p>
  
  <p>I know that to force make to compile version.c always regardless of modification date I can <code>touch version.c</code>.</p>
  
  <p>Is there a makefile only way to achieve this? If I write <code>.PHONY : version.o</code> the object file doesn't get build at all.</p>
  
  <p><strong>EDIT:</strong>
  Here is my makefile:</p>
  
  <pre><code>export CC = gcc
  
  
  export MODULES = $(sort \
       sys \
       cim \
       version \
  )
  
  export FILES = $(sort \
               main.c \
               cim.c \
               version.c \
  )
  
  VPATH = $(MODULES)
  
  OBJS = $(FILES:.c=.o)
  
  INCLUDES = $(addprefix -I,$(MODULES))
  
  all:$(OBJS)
      $(CC) $(INCLUDES) $(OBJS) -o main.exe
  
  
  clean:
      rm -rf *.o *.exe
  
  cim.o: cim.c
  main.o: main.c cim.o
  version.o: version.c
  
  .PHONY: version.o
  
  .c.o :
      $(CC) $(CFLAGS) $(INCLUDES) -c $&lt;
  </code></pre>