title: How to use clock gating in RTL?
body: <p>I am clock gating some <strong>latch</strong> and logic in my design. I don't have much experience in synthesis and place &amp; route. What is the proper way to implement clock gating in RTL? </p>
  
  <p>Example1:</p>
  
  <pre><code>always_comb begin
      gated_clk  = clk &amp; latch_update_en;
  end
  
  always_latch begin
      if(gated_clk) begin
           latch_data &lt;= new_data;
      end
  end
  </code></pre>
  
  <p>Example2:
  I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this:</p>
  
  <pre><code>clock_gator cg_cell (.clk(clk), .en(latch_update_en), .scan_en(scan_en_in), .gated_clk(gated_clk));
  
  always_latch begin
      if(gated_clk) begin
           latch_data &lt;= new_data;
      end
  end
  </code></pre>
  
  <p>What is the purpose of using custom clock gating cell? Does the tool have hard time in synthesis if clk is directly "and"-ed in a always_comb block with another enable signal? I am having a feeling that using special clock gating cell is a standard approach to generated gated clock signal. I am trying to understand why this is the case. </p>