title: Execution in verilog sequentially or concurrently
body: <p>I am new to verilog and am finding the execution of verilog tricky. How does the execution occurs in a verilog program. Say I have 2 modules and a testbench-</p>
  
  <pre><code>module module1(clock,A,B,C);
      input A,B,clock;
      output C;
      assign c=A+B;
  endmodule
  
  module module2(clock,A,B,C);
      input A,B,clock;
      output C;
  
      assign C=A-B;
  
  endmodule
  
  module testbench;
      reg A,B,clock;
      wire C;
      module1 m1(clock,A,B,C);
      module2 m2(clock,A,B,C);
      initial
          clock=1'b0;
      always
          #4 clock=~clock;
  endmodule
  </code></pre>
  
  <p>I understand all initial blocks start at time 0.But are these initial blocks then executed sequentially i.e. if a initial block has more than one lines, will all of them executed sequentially or concurrently. Also, how does module execution take place?Will <code>module1</code>  start first as it appears before <code>module2</code> in testbench and finish completely and then <code>module2</code>  start or both run concurrently. What happens when clock changes after 4sec, will the module running stop in between if clock changes or will it complete its previous execution and then start again with new clock?</p>