title: Initial value of unsigned in VHDL
body: <p>I am using Altera Max plus II, writing in VHDL. </p>
  
  <p>In the architecture I am given this command: </p>
  
  <pre><code>signal count_value : unsigned (3 downto 0);
  </code></pre>
  
  <p>I noticed that the initial value of count_value is 0000. 
  How can I change it? </p>
  
  <p>EDIT: </p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all ;
  
  entity decade_counter is
     port ( clk : in std_logic;
     q : out unsigned(3 downto 0) );
  end entity decade_counter;
  
  architecture rtl of decade_counter is
    signal count_value : unsigned(3 downto 0);
    begin
      count : process (clk) is
      begin
      if rising_edge(clk) then
        if count_value = 9 then
           count_value &lt;= "0000";
        else
           count_value &lt;= count_value + 1;
       end if;
     end if;
     end process count;
     q &lt;= count_value;
  end architecture rtl;
  </code></pre>
  
  <p>I have this code which is a BCD Counter from 1 to 9. I want to modify it so that it goes from 7 to 12. That's the reason why I want count_value to initialize at 0111.</p>
  
  <p>Thanks in advance</p>