title: in VHDL, how to assign list of output ports to an array?
body: <p>I have an entity that has hundreds of output such as tap0(15 downto 0), tap1(15 downto 0), ..., tap200(15 downto 0)</p>
  
  <p>For each iteration, I would like to assign four of those outputs to a complex multiplier entity that has four inputs.</p>
  
  <p>For example:
  on 1st iteration:</p>
  
  <pre><code>mult_in_A &lt;= tap0;
  mult_in_B &lt;= tap1;
  mult_in_C &lt;= tap2;
  mult_in_D &lt;= tap3;
  </code></pre>
  
  <p>on 2nd iteration:</p>
  
  <pre><code>mult_in_A &lt;= tap4;
  mult_in_B &lt;= tap5;
  mult_in_C &lt;= tap6;
  mult_in_D &lt;= tap7;
  </code></pre>
  
  <p>On 3rd iteration:</p>
  
  <pre><code>mult_in_A &lt;= tap8;
  mult_in_B &lt;= tap9;
  mult_in_C &lt;= tap10;
  mult_in_D &lt;= tap11;
  </code></pre>
  
  <p>and so on...</p>
  
  <p>How do I make the code above more efficient by having some kind of for loop and putting those output ports to an array? So that I can write the code as following:</p>
  
  <pre><code>mult_in_A &lt;= tap_array(i);
  mult_in_A &lt;= tap_array(i+1);
  mult_in_A &lt;= tap_array(i+2);
  mult_in_A &lt;= tap_array(i+3);
  </code></pre>
  
  <p>Updated:</p>
  
  <p>Here is the code example</p>
  
  <pre><code>ARCHITECTURE rtl_syn OF fir_filter_cntl IS
  
  COMPONENT delay_line
  PORT(
      aclr        : IN STD_LOGIC;
      clock       : IN STD_LOGIC;
      clken       : IN STD_LOGIC;
      shiftin     : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
      shiftout    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      taps0x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      taps1x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      taps2x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      taps3x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      ...
      taps128x    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      taps129x    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
  END COMPONENT;
  
  TYPE samples IS array (0 to 129) of std_logic_vector(15 downto 0);
  SIGNAL sample_i: samples;
  
  BEGIN
  
  delay_line_i1 : delay_line
      PORT MAP (
      aclr        =&gt; rx_reset,
      clock       =&gt; rx_clock,
      clken       =&gt; i_clken,
      shiftin     =&gt; i_sample,
      shiftout    =&gt; open,
      taps0x      =&gt; sample_i(0),  -- &lt;- this doesn't work. In simulation,
                                   -- I observed taps0x output has some valid
                                   -- values, but sample_i's value is unknown
      taps1x      =&gt; sample_i(1),
      taps2x      =&gt; sample_i(2),
      ...
      taps129x    =&gt; sample_i(129));
  </code></pre>
  
  <p>Then down below in some process I have the following:</p>
  
  <pre><code>sample_counter      &lt;= (others =&gt; '0');
  
  CASE device_number IS
      WHEN "000" =&gt;
          complex_mult_0I_in  &lt;= sample_i(conv_integer(sample_counter+0)); 
          complex_mult_1I_in  &lt;= sample_i(conv_integer(sample_counter+1));
          complex_mult_2I_in  &lt;= sample_i(conv_integer(sample_counter+2));
          complex_mult_3I_in  &lt;= sample_i(conv_integer(sample_counter+3));
  </code></pre>
  
  <p>Several questions:<br>
  1. Why did the following port assignment work?
  taps0x      => sample_i(0)
  <br>
  2. How can I use for..loop or for..generate to simplify the following codes?</p>
  
  <blockquote>
  <pre><code>taps0x =&gt; sample_i(0),
  taps1x =&gt; sample_i(1), 
  taps2x =&gt; sample_i(2),
  taps3x =&gt; sample_i(3),
  taps4x =&gt; sample_i(4), 
  taps5x =&gt; sample_i(5),
  and so on.
  </code></pre>
  </blockquote>