title: Generating post-synthesis verilog model in Quartus II
body: <p>I have Xilinx background and now I happened to write some code on Altera devices. I have a question about generating post-synthesis models (also post-fit). On Xilinx I had <code>netget</code> which was able to generate verilog or vhdl post-synthesis model of my design which I was able to use freely for example in iverilog compiler. I quartus ii i have found <code>quartus_eda</code> tool but I am not able to perform what I wanted, I can generate <code>*.vo</code> files which looks fine but I am not able to find libraries to cover elements used there. I am using <code>--tool=modelsim</code>. Where I should look after them ?</p>