title: How can I achieve something similar to Xilinx' RLOC in Altera FPGAs?
body: <p>I have so far not found any way to do anything similar to Xilinx' RLOC constraints for Altera FPGAs. </p>
  
  <p>Does anyone know a way to do this? </p>
  
  <p>For example place two FFs in the same or adjacent LABs </p>