title: Makefile rebuilds everything every time, why?
body: <p>I have simple makefile here:</p>
  
  <pre><code>SOURCES= $(wildcard *.c)
  OBJECTS= $(patsubst %.c, %.o, $(SOURCES))
  NAMES= $(patsubst %.c, %, $(SOURCES))
  CC=gcc
  CFLAGS= -Wall -c -o     
  TASKS_IN_DIRS= $(addprefix obj/,$(OBJECTS)) $(addprefix bin/,$(NAMES))
  
  all: $(NAMES)
  
  $(NAMES): %: %.o $(OBJECTS)
      $(CC) -o bin/$@ obj/$^
  $(OBJECTS): %.o: %.c 
      $(CC) $(CFLAGS) obj/$@ $&lt;
  clean:
      rm -rf $(TASKS_IN_DIRS)
  </code></pre>
  
  <ol>
  <li>Getting all the c files names.</li>
  <li>Making from them simple names(without extension) and object names.</li>
  <li>Doing things</li>
  </ol>
  
  <p>And what matters - all works, but works every time i print make(compiling and linking all the files). even if i don't changed anything and i do it few times in row, is something wrong with dependencies? </p>
  
  <p>I expected something like "blabla is up to date" instead.</p>