title: Can extensive usage of L3 cache by one core invalidate L1/L2 cache of another core?
body: <p>Current Intel CPU cache architecture consists of local L1 and L2 caches and shared inclusive L3 cache. I have two similar questions regarding this:</p>
  
  <ol>
  <li>Can extensive memory access by the thread running on one core invalidate L1/L2 cache of another core?</li>
  <li>Can data required by thread running on a single core occupy the whole L3 cache?</li>
  </ol>
  
  <p>UPDATE: <strong>Be aware that Intel Skylake has new L3 cache architecture which is non-inclusive.</strong></p>