title: Use a singnal as an input or output in VHDL
body: <p>I write this code . I want to use data as an output when r = '1' and input when w = '1'. I try inout but it doesn't work. and it had an error (Error: D:/modelism project/project/memory.vhd(42): Target of signal assignment is not a signal.). Can you help me to fix it ?</p>
  <pre><code>use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  ----------------------------------------------------------------------
  Entity memory is
      Generic (bits: integer := 16;
           words: integer := 16);
      port (  r, w: in std_logic;-------read and write------------
          addr: in std_logic_vector(11 downto 0);
          data: inout std_logic_vector(bits-1 downto 0));
  
  End memory;
  ----------------------------------------------------------------------
  Architecture memory of memory is
      Type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0);
      constant memory: vector_array :=
                      ( &quot;0000000000000000&quot;,
                        &quot;0000000000000001&quot;,
                        &quot;0000000000000010&quot;,
                        &quot;0000000000000011&quot;,
                        &quot;0000000000000100&quot;,
                        &quot;0000000000000101&quot;,
                        &quot;0000000000000110&quot;,
                        &quot;0000000000000111&quot;,
                        &quot;0000000000000000&quot;,
                        &quot;0000000000000001&quot;,
                        &quot;0000000000000010&quot;,
                        &quot;0000000000000011&quot;,
                        &quot;0000000000000100&quot;,
                        &quot;0000000000000101&quot;,
                        &quot;0000000000000110&quot;,
                        &quot;0000000000000111&quot;);
      signal loc: integer range 0 to words - 1;
  begin
      process(r, w)
      begin
          if(r = '1') then
              loc &lt;= to_integer(signed(addr));
              data &lt;= memory(loc);
          elsif(w = '1') then
              loc &lt;= to_integer(signed(addr));
              memory(loc) &lt;= data;
          end if;
      end process;
  End memory;
  </code></pre>