title: Signal <signal> cannot be synthesized, bad synchronous description
body: <p>I'm trying to implement a component that takes in input a base clock and as output a pattern accordingly to this scheme:</p>
  
  <p><a href="https://i.stack.imgur.com/yk7hD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yk7hD.png" alt="enter image description here"></a></p>
  
  <p>I'm getting this error, and i've tried to fix it in many ways following various suggestion also from stackoverflow, but nothing...</p>
  
  <blockquote>
    <p><strong>ERROR:Xst:827</strong> - "E:/Progetti/nuovi/Clock_generator/CG_ex_3/clock_ex3.vhd" line 34: Signal <strong><em>check_0</em></strong> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.</p>
  </blockquote>
  
  <p>Some times the same error refer to <strong><em>pre_forma_clk</em></strong></p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity clock_ex3 is
      Port ( base_clk : in  STD_LOGIC;
             forma_clk : out  STD_LOGIC);
  end clock_ex3;
  
  architecture Behavioral of clock_ex3 is
      signal pre_forma_clk : std_logic := '0';
  begin
  
  forma_clk &lt;= pre_forma_clk;
  
  pattern_generator : process(base_clk)  --line 34
  
      variable check_0 : natural := 0;
      variable check_1 : natural := 0;
      variable check_2 : natural := 0;
      variable check_3 : natural := 0;
  
  begin
      if (rising_edge(base_clk)) then
          check_0 := check_0 + 1;
          if (check_0 = 15) then
              pre_forma_clk &lt;= not pre_forma_clk;
          end if;
      end if;
  
      if (falling_edge(base_clk) and check_0 &gt;= 15) then
          check_1 := check_1 + 1;
          if (check_1 = 10) then
              pre_forma_clk &lt;= not pre_forma_clk;
          end if;
      end if;
  
      if (falling_edge(base_clk) and check_1 &gt;= 10) then
          check_2 := check_2 + 1;
          if (check_2 = 15) then
              pre_forma_clk &lt;= not pre_forma_clk;
          end if;
      end if;
  
      if (rising_edge(base_clk) and check_2 &gt;= 15) then
          check_3 := check_3 + 1;
          if (check_3 = 10) then
              pre_forma_clk &lt;= not pre_forma_clk;
              check_0 := 0;
              check_1 := 0;
              check_2 := 0;
              check_3 := 0;
          end if;
      end if;
  
  end process;
  
  end Behavioral;
  </code></pre>
  
  <p>I've already tried to separate IF conditions in different IFs...
  thanks for help</p>