title: should PciE reads (non posted) be done in napi context (sirq)
body: <p>we have a custom driver to a FPGA that implements multiple devices. the network devices use NAPI. in the NAPI poll routine I have to read some registers from the FPGA. 
  We notice that we are spending a large amount of cpu time in sirq, and other device access is delayed.</p>
  
  <p>My question is that since a read from the FPGA is a non posted read (requiring a wait for the returned data) is this violating the no block rule of the sirq context. Maybe the packet processing should be done in a tasklet ?</p>
  
  <p>I found that if I moved one of the devices to it's own driver, and that device only writes to the FPGA (posted write) the performance of that device improves. I am being asked for an explanation of that result.</p>