title: VHDL - unconnected components in top module
body: <p>I am working on a project and I'm failing to connect the components in the top module.
  I just can't see what I'm doing wrong. Any suggestions are highly appreciated.</p>
  
  <p>Besides not being able to see the components in the RTL schematic, I get some warnings:</p>
  
  <pre><code>WARNING:Xst:1290 - Hierarchical block &lt;u0&gt; is unconnected in block &lt;TOP&gt;.
     It will be removed from the design.
  WARNING:Xst:1290 - Hierarchical block &lt;u1&gt; is unconnected in block &lt;TOP&gt;.
     It will be removed from the design.
  
  WARNING:Xst:2677 - Node &lt;u1/calc_deb&gt; of sequential type is unconnected in block &lt;TOP&gt;.
  WARNING:Xst:2677 - Node &lt;u1/flipflops_1&gt; of sequential type is unconnected in block &lt;TOP&gt;.
  WARNING:Xst:2677 - Node &lt;u1/flipflops_0&gt; of sequential type is unconnected in block &lt;TOP&gt;.
  </code></pre>
  
  <p>So here is the implementation of the top module:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  
  entity TOP is
  port(
      calc: in std_logic;
      OP: in std_logic_vector(1 downto 0);
      inValue: in std_logic_vector(3 downto 0);
      clk: in std_logic
      );
  end TOP;
  
  architecture Behavioral of TOP is
  
  component alu port(
          OP : in  std_logic_vector(1 downto 0);
        inValue : in  std_logic_vector(3 downto 0);
        regValue : in  std_logic_vector(3 downto 0);
        result: out std_logic_vector(4 downto 0);
        clk : in  STD_LOGIC
          );
  end component;
  
  component debouncer port(
      calc : in  STD_LOGIC;
      calc_deb : out  STD_LOGIC;
      clk: in std_logic
  );  
  end component;
  
  signal calc_debaux: std_logic;
  signal regValueaux: std_logic_vector(3 downto 0);
  signal resultaux: std_logic_vector(4 downto 0);
  --signal OP: std_logic_vector(1 downto 0);
  --signal OP: std_logic_vector(3 downto 0);
  
  
  begin
  
  u0: alu port map(OP =&gt; OP,  inValue=&gt;inValue,   regValue=&gt;regValueaux,  result=&gt;resultaux, clk=&gt;clk);
  
  u1: debouncer PORT MAP(calc=&gt;calc, alc_deb=&gt;calc_debaux, clk=&gt;clk);
  
  end Behavioral;
  </code></pre>
  
  <p>And here are the two entities that I'm instantiating in the top module:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity ALU is
      Port ( OP : in  std_logic_vector(1 downto 0);
             inValue : in  std_logic_vector(3 downto 0);
             regValue : in  std_logic_vector(3 downto 0);
             result: out std_logic_vector(4 downto 0);
             clk : in  STD_LOGIC
                );
  end ALU;
  
  architecture archi of alu is
  
  signal res_temp: std_logic_vector(4 downto 0);
  signal aux1, aux2: std_logic_vector(4 downto 0);
  
  begin
  
  aux1 &lt;= ('0' &amp; inValue);
  aux2 &lt;= ('0' &amp; regValue);
  result &lt;= res_temp; 
  
  process (inValue, OP)
  begin
          case OP is
              when "00" =&gt;
                  res_temp &lt;=  (aux1) + (aux2) ;
              when "01" =&gt;
                  res_temp &lt;= aux1 - aux2; 
              when "10" =&gt;
                  res_temp &lt;= (inValue and regValue);
              when others =&gt;
                  res_temp &lt;= '0' &amp; (regValue(0) &amp; regValue(3 downto 1));   
          end case;
  end process;
  end archi ; 
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  
  entity debouncer is
      Port ( calc : in  STD_LOGIC;
             calc_deb : out  STD_LOGIC;
                clk: in std_logic);
  end debouncer;
  
  architecture Behavioral of debouncer is
    SIGNAL flipflops   : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
    SIGNAL counter_set : STD_LOGIC;                    --sync reset to zero
    SIGNAL counter_out : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS =&gt; '0'); --counter output
  BEGIN
  
    counter_set &lt;= flipflops(0) xor flipflops(1);   --determine when to start/reset counter
  
    PROCESS(clk)
    BEGIN
      IF(clk'EVENT and clk = '1') THEN
        flipflops(0) &lt;= calc;
        flipflops(1) &lt;= flipflops(0);
        If(counter_set = '1') THEN                  --reset counter because input is changing
          counter_out &lt;= (OTHERS =&gt; '0');
        ELSIF(counter_out(8) = '0') THEN --stable input time is not yet met
          counter_out &lt;= counter_out + 1;
        ELSE                                        --stable input time is met
          calc_deb &lt;= flipflops(1);
        END IF;    
      END IF;
    END PROCESS;
  
  end Behavioral;
  </code></pre>
  
  <p>I also get some more warnings:</p>
  
  <pre><code>Synthesizing Unit &lt;TOP&gt;.
      Related source file is "D:/Mestrado/1o ano/1o semestre/PSD/Projectos/andgates/TOP.vhd".
  WARNING:Xst:646 - Signal &lt;resultaux&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  WARNING:Xst:653 - Signal &lt;regValueaux&gt; is used but never assigned. This sourceless signal will be automatically connected to value 0000.
  WARNING:Xst:646 - Signal &lt;calc_debaux&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  Unit &lt;TOP&gt; synthesized.
  </code></pre>
  
  <p>I have spend a huge time in this (this is part of a bigger project, I'm just trying to restart by going piece by piece to facilitate troubleshooting) and I am now clueless. :(</p>
  
  <p>Thank you for your time.</p>