title: Clock divider in vhdl from 100MHz to 1Hz code
body: <p>I wrote this code for dividing the clock an a nexys4 fpga that has its integrated clock at 100Mhz frequency by default , and i need to divide it to 1hz. Can someone tell me if its correct or if not what needs to be changed ?</p>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  
  
  entity digi_clk is
  port (clk1 : in std_logic;
         clk : out std_logic
       );
  end digi_clk;
  
  architecture Behavioral of digi_clk is
  
  signal count : integer :=0;
  signal b : std_logic :='0';
  begin
  
   --clk generation.For 100 MHz clock this generates 1 Hz clock.
  process(clk1) 
  begin
  if(rising_edge(clk1)) then
  count &lt;=count+1;
  if(count = 50000000) then
  b &lt;= not b;
  count &lt;=0;
  
  end if;
  end if;
  clk&lt;=b;
  end process;
  end;
  </code></pre>