title: How to remove I/O port declarations using regexp in verilog mode
body: <p>I'm trying to instantiate <code>abc_d</code> module and i don't want all of its ports to be declared as I/O ports in <code>abc</code> top module. I want to exclude <code>ex_out_port</code> to be declared as <code>output</code> port. </p>
  
  <pre><code>module abc(/*AUTOARG*/);
  /*AUTOINPUT*/
  /*AUTOOUTPUT*/
  /*AUTOWIRE*/
  abc_d u_abc_d(/*AUTOINST*/);
  endmodule
  //Localvariables:
  //verilog-auto-output-ignore-regexp:("ex_out_port")
  //END:
  </code></pre>
  
  <p>expected code: </p>
  
  <pre><code> module abc (/*AUTOARG*/
   /Inputs
   input port1;
   input port2;
   /Outputs
   output port3;
   output port4;
   /*AUTOWIRE*/
   wire ex_out_port;
  
   //Instance
   abc_d u_abc_d(/*AUTOINST*/
   .port1 (port1),
   .port2 (port2),
   .port3 (port3),
   .port4 (port4),
   .ex_out_port (ex_out_port)):
  endmodule
  </code></pre>
  
  <p>Related already-answered questions:</p>
  
  <ul>
  <li><a href="https://stackoverflow.com/q/2653055">Using Regular Expressions for Verilog Port Mapping</a></li>
  <li><a href="https://stackoverflow.com/q/31184100">using emacs auto&#39;s to instansiate a stub module (inputs=0, outputs=[]</a></li>
  </ul>