title: Why do I get undefined output vectors and an undefined clock when simulating?
body: <p>I am pretty new to VHDL and am encountering an error with my testbench (at least I believe its only in the testbench).
  My programme simulates a stadium with 12 sections. The programme consists of 12 individual counters along with LEDs when 90% of max capacity is reached and a digital 4 digit display that displays the total of all 12 counters.</p>
  <p>Whenever I try to compile the code, there is no change in any of the outputs and all of the inputs are undefined.</p>
  <p>Any advice would be appreciated.</p>
  <p>Architecture:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.Numeric_STD.all;
  
  entity counter is
  
  Port (Clk: in STD_LOGIC;
        Enable : in STD_LOGIC_Vector(11 downto 0);
        Reset : in STD_LOGIC_Vector(11 downto 0);
        Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12 : out STD_LOGIC_Vector(8 downto 0); -- 9 bits as 300 &lt;2^9
        Qt : out STD_LOGIC_Vector(11 downto 0); -- 12 bits as 300 (section) * 12 &gt; 2^12
        a,b,c,d,e,f,g : out STD_LOGIC_Vector(3 downto 0); --Individual segments of the display (4 because the number will max out at 3600)
        Led0,Led1,Led2,Led3,Led4,Led5,Led6,Led7,Led8,Led9,Led10,Led11 : out STD_LOGIC);
  end counter;      
        
  
  Architecture behavioral of counter is
      
      type REG_variable is array(0 to 11) of unsigned(8 downto 0);
      type Q_variable is array (0 to 11) of STD_LOGIC_Vector(8 downto 0);
      type DIGITS_variable is array (0 to 3) of unsigned (3 downto 0);
      
      signal output_array : Q_variable;
      signal LED_Output : STD_LOGIC_Vector(11 downto 0);
      
      
      component count_comp is
          Port(Clk, Reset, Enable : in STD_Logic;
          Q : out STD_LOGIC_Vector(8 downto 0);
          LED : out STD_LOGIC);
      end component; 
      
  begin 
      process (CLK,Reset)
          variable LED_lights : STD_LOGIC_Vector(11 downto 0) := (others =&gt; '0');
          variable REG : REG_variable := (others =&gt;(others =&gt; '0'));
          variable Total_REG: unsigned(11 downto 0) := (others =&gt; '0');
          variable Digits : DIGITS_variable := (others =&gt; (others =&gt; '0'));
      
  begin 
  Single_Counter : for i in 11 downto 0 loop
     if Reset(i) = '1' then
     Total_REG := Total_REG - REG(i);
     REG(i) := (others =&gt; '0');
     LED_lights(i) := '0';
         elsif rising_edge(CLK) then
               if Enable(i) = '1' and (REG(i) &lt;= 300) then
               if (REG(i) &gt;= 270) then
                    LED_lights(i) := '1';
                    Total_REG := Total_REG + 1;
                    REG(i) := REG(i)+ 1;
               end if;   
           
  Digits(0) := to_unsigned(to_integer(Total_REG - Total_REG mod 100),4);
  Digits(1) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/10),4);
  Digits(2) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/100),4);
  Digits(3) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/1000),4);
  
  end if;
  end if;
  
  Qt &lt;= STD_LOGIC_Vector(Total_REG);
  output_array(i) &lt;= STD_LOGIC_Vector(REG(i));
  LED_output(i) &lt;= LED_lights(i);
  
  
  for x in 3 downto 0 loop
  case to_integer(Digits(x)) is
  
      when 0
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '1'; f(x) &lt;= '1'; g(x) &lt;= '0';
       
      when 1
      =&gt; a(x) &lt;= '0'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '0'; e(x) &lt;= '0'; f(x) &lt;= '0'; g(x) &lt;= '0';
      
      when 2 
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '0'; d(x) &lt;= '1'; e(x) &lt;= '1'; f(x) &lt;= '0'; g(x) &lt;= '1';
      
      when 3 
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '0'; f(x) &lt;= '0'; g(x) &lt;= '1';
      
      when 4
      =&gt; a(x) &lt;= '0'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '0'; e(x) &lt;= '0'; f(x) &lt;= '1'; g(x) &lt;= '1';
      
      when 5
       =&gt; a(x) &lt;= '1'; b(x) &lt;= '0'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '0'; f(x) &lt;= '1'; g(x) &lt;= '1';
      
      when 6 
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '0'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '1'; f(x) &lt;= '1'; g(x) &lt;= '1';
      
      when 7 
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '0'; e(x) &lt;= '0'; f(x) &lt;= '0'; g(x) &lt;= '0';
      
      when 8
       =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '1'; f(x) &lt;= '1'; g(x) &lt;= '1';
      
      when 9
      =&gt; a(x) &lt;= '1'; b(x) &lt;= '1'; c(x) &lt;= '1'; d(x) &lt;= '1'; e(x) &lt;= '0'; f(x) &lt;= '1'; g(x) &lt;= '1';
      
      when others
      =&gt; a(x) &lt;= '0'; b(x) &lt;= '0'; c(x) &lt;= '0'; d(x) &lt;= '0'; e(x) &lt;= '0'; f(x) &lt;= '0'; g(x) &lt;= '0';
      
     end case; 
     end loop;
  end loop;   
  end process;
  
  Counters : for i in 11 downto 0 generate
     counter_gen : count_comp
     port map (CLK =&gt; CLK, Reset =&gt; Reset (i), Enable =&gt; Enable(i), Q =&gt; output_array(i), LED =&gt; LED_output(i));
  end generate;
      
  Q1 &lt;= output_array(0);
  Q2 &lt;= output_array(1);
  Q3 &lt;= output_array(2);
  Q4 &lt;= output_array(3);
  Q5 &lt;= output_array(4);
  Q6 &lt;= output_array(5);
  Q7 &lt;= output_array(6);
  Q8 &lt;= output_array(7);
  Q9 &lt;= output_array(8);
  Q10 &lt;= output_array(9);
  Q11 &lt;= output_array(10);
  Q12 &lt;= output_array(11);
  
  Led0 &lt;= LED_output(0);
  Led1 &lt;= LED_output(1);
  Led2 &lt;= LED_output(2);
  Led3 &lt;= LED_output(3);
  Led4 &lt;= LED_output(4);
  Led5 &lt;= LED_output(5);
  Led6 &lt;= LED_output(6);
  Led7 &lt;= LED_output(7);
  Led8 &lt;= LED_output(8);
  Led9 &lt;= LED_output(9);
  Led10 &lt;= LED_output(10);
  Led11 &lt;= LED_output(11);
  
  end behavioral;
  </code></pre>
  <p>Testbench:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Project_Testbench is
  end;
   
  architecture TB1 of Project_Testbench is
   
         component count_comp is
        Port(Clk: in STD_LOGIC;
           Enable : in STD_LOGIC_Vector(11 downto 0);
           Reset : in STD_LOGIC_Vector(11 downto 0);
           Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12 : out STD_LOGIC_Vector(8 downto 0);
           Qt : out STD_LOGIC_Vector(11 downto 0);
           a,b,c,d,e,f,g : out STD_LOGIC_Vector(3 downto 0);
           Led0,Led1,Led2,Led3,Led4,Led5,Led6,Led7,Led8,Led9,Led10,Led11 : out STD_LOGIC);
      end component count_comp; 
       
       signal Clk_TB : std_logic := '0';
       signal Enable : std_logic_Vector(11 downto 0) := (others =&gt; '0');
       signal Reset : std_logic_Vector(11 downto 0) := (others =&gt; '0');
  
  begin 
  
       Clk_TB &lt;= not Clk_TB after 5ns;
  
      
  stimuli: process
       
          begin
  
           Enable &lt;= &quot;000000000000&quot;; Reset &lt;= &quot;11111111111&quot;;
           wait for 100 ns;
           
           Enable &lt;= &quot;11111111111&quot;; Reset &lt;= &quot;00000000000&quot;;
           wait for 200 ns;
           
           Enable &lt;= &quot;11110011111&quot;; Reset &lt;= &quot;00000000000&quot;;
           wait for 50 ns;
           
           Enable &lt;= &quot;00011111111&quot;; Reset &lt;= &quot;00000000000&quot;;
           wait for 20 ns;
           
           Enable &lt;= &quot;11111111111&quot;; Reset &lt;= &quot;11000000000&quot;;
           wait for 20 ns;
           
           Enable &lt;= &quot;11111111111&quot;; Reset &lt;= &quot;00000000000&quot;;
           wait for 1000 ns;
  
          
          wait;
          
          end process;
  
  uut: count_comp port map
      (
       Clk =&gt; Clk_TB,
       Enable =&gt; Enable,
       Reset =&gt; Reset);
        
   
       
  end;
  </code></pre>
  <p>Here is a screenshot of the output signals.
  <a href="https://i.stack.imgur.com/0rGwJ.png" rel="nofollow noreferrer">Output Signals</a></p>