title: Assign ASCII character to wire in Verilog
body: <p>I understand that you can declare a string in a Verilog test bench as follows:</p>
  
  <pre><code>reg [8*14:1] string_value;  
  
  initial 
      string_value = "Hello, World!";
  </code></pre>
  
  <p>I can then do things with this string, like use <code>$display</code> in a test bench to display it.</p>
  
  <p>I haven't been successful in doing the same in a module when I flash it to my FPGA: </p>
  
  <pre><code>reg [8*14:1] string_value;  
  
  always @(reset) 
  begin
      string_value = "Hello, World!";
      // Do stuff with string value
  </code></pre>
  
  <p>Even assigning a single value does not work:</p>
  
  <pre><code>reg [8:1] char_value;  
  
  always @(reset) 
  begin
      char_value = "A";
      if (char_value == 8'h41)
          // Do stuff!
  </code></pre>
  
  <p>I want to shift the individual characters on an 8-bit bus to an LCD screen for display.</p>
  
  <p>How can I work with strings in Verilog?</p>