title: unsigned to integer conversion VHDL
body: <p>I'm trying to convert an <code>unsigned(7 downto 0)</code> data to an integer!</p>
  
  <p>I have this</p>
  
  <pre><code>SIGNAL SQ_X1: INTEGER RANGE 0 TO 1024:= conv_integer(pos_ini_x);
  </code></pre>
  
  <p>where <code>pos_ini_x</code> comes from another module that is the result of a random number calculation. Syntax issues are good but when I convert to assign to <code>SQ_X1</code> variable, it doesn't work well, it always provide a zero as a result.</p>
  
  <p>If you know how to improve this conversion and resolve this problem and explain why it happens, could you help me please?</p>
  
  <p>It would be appreciated.</p>