title: What does 'include and 'define means? and what do they do?
body: <p>I'm new in system Verilog, and I'm going through a .svh file. In he script there are lines that states the use of 'include and 'define and sometimes even 'ifndef, for example:</p>
  
  <blockquote>
    <p>'include CHECK_A</p>
  </blockquote>
  
  <p>and also </p>
  
  <blockquote>
    <p>'define CHECK_B</p>
  </blockquote>
  
  <p>What does the apostrophe means? and what does each of them do? </p>