title: Implement VHDL/Verilog only using lookup tables in Xilinx ISE
body: <p>Is there any way of telling ISE to synthesize my VHDL/Verilog code into combinational circuits consisting only of look-up tables? I would like to avoid multiplexers, multipliers, and the like in the tech schematic... and wouldn't mind having an unoptimized (with many components than is optimal) version because of this preference. </p>
  
  <p>Thanks SOCommunity!</p>