title: Unknown verilog error 'expecting "endmodule"'
body: <p>In verilog I have an error that I can't get past. this is the first bit of the code then the last bit</p>
  
  <blockquote>
  <pre><code> module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype);
    input[5:0] op,funct;
    output[2:0] aluop;
    output[1:0] btype;
    output mwr,mreg,mrd,alusrc,regdst,regwr;
    wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype;
    case(op)
        6'b000000: begin
            case(funct)
                6'b001010:
                    assign aluop = 3'b010;
                6'b001100:
                    assign aluop = 3'b111;
                6'b010001:
                    assign aluop = 3'b011;
                default:
                    assign aluop = 3'b000;          
            endcase
            assign btype = 2'b00;
            assign mwr = 1'b0;
            assign mreg = 1'b0;
            assign mrd = 1'b0;
            assign alusrc = 1'b0;
            assign regdst = 1'b1;
            assign regwr = 1'b1;
            end
  </code></pre>
  </blockquote>
  
  <p>...</p>
  
  <blockquote>
  <pre><code>  default: begin
        assign aluop = 3'b000;
          assign mwr = 0;
          assign mreg = 0;
          assign mrd = 0;
          assign alusrc = 0;
          assign btype = 2'b00;
          assign regdst = 0;
          assign regwr = 0;
          end
  endcase
  </code></pre>
    
    <p>endmodule</p>
  </blockquote>
  
  <p>it keeps giving me the following errors</p>
  
  <p>Error (10170): Verilog HDL syntax error at Decoder.v(7) near text "case";  expecting "endmodule"
  Error (10170): Verilog HDL syntax error at Decoder.v(14) near text "6";  expecting "endmodule"</p>
  
  <p>It also does this at every end statement and default and endcase</p>
  
  <p>I have no idea why it's doing this, I'm fairly new to verilog.</p>
  
  <p>thanks in advance</p>