title: Can I force cache coherency on a multicore x86 CPU?
body: <p>The other week, I wrote a little thread class and a one-way message pipe to allow communication between threads (two pipes per thread, obviously, for bidirectional communication).  Everything worked fine on my Athlon 64 X2, but I was wondering if I'd run into any problems if both threads were looking at the same variable and the local cached value for this variable on each core was out of sync.</p>
  
  <p>I know the <em>volatile</em> keyword will force a variable to refresh from memory, but is there a way on multicore x86 processors to force the caches of all cores to synchronize?  Is this something I need to worry about, or will <em>volatile</em> and proper use of lightweight locking mechanisms (I was using _InterlockedExchange to set my volatile pipe variables) handle all cases where I want to write "lock free" code for multicore x86 CPUs?</p>
  
  <p>I'm already aware of and have used Critical Sections, Mutexes, Events, and so on.  I'm mostly wondering if there are x86 intrinsics that I'm not aware of which force or can be used to enforce cache coherency.</p>