title: vhdl equivalent for initial block in verilog
body: <p>I am trying to convert some Verilog code to VHDL. I have difficulties to translate initial block in Verilog to VHDL properly. </p>
  
  <p>As far as I know, the initial block corresponds to the process statement without a sensitivity list but we have to add a "wait" statement before the "end process".I tried it but it did not work. I tried some other methods too (using exit clause, conditional clause ( wait until), "for- generate"  without process, etc) but none was successful.</p>
  
  <p>Here is the Verilog code I want to convert, and it works properly</p>
  
  <pre><code>module MyRAM  #(parameter DATA_WIDTH=24, parameter ADDR_WIDTH=10)
  (
  input [(DATA_WIDTH-1):0] data,
  input [(ADDR_WIDTH-1):0] read_addr, write_addr,
  input we, clk,
  output reg [(DATA_WIDTH-1):0] q
  );
  
  // Declare the RAM variable
  reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
  
  initial 
  begin : INIT
      integer i;
  
  
      for(i = 1; i &lt; ((2**ADDR_WIDTH)-1); i = i+1) begin
          if (i == 132)   ram[i]   = 24'h550000;
          else if (i == 133)  ram[i]   = 24'h005500;
          else if (i == 134)  ram[i]   = 24'h000055;
          else    ram[i]   = 24'h000000;
      end
      //*/
  end 
  
  always @ (negedge clk)
  begin
      // Write
      if (we)
          ram[write_addr] &lt;= data;
          q &lt;= ram[read_addr];
  end
  
  endmodule
  </code></pre>
  
  <p>and this is the VHDL code I have written so far:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  
  entity MyRAM is 
  generic
  (DATA_WIDTH: integer;
  ADDR_WIDTH: integer);
  
  port
  (
  data :in std_logic_vector ((DATA_WIDTH-1) downto 0);
  read_addr :in std_logic_vector((ADDR_WIDTH-1) downto 0);
  write_addr :in std_logic_vector(( DATA_WIDTH-1) downto 0);
  we :in std_logic;
  clk :in std_logic;
  q :out std_logic_vector( 23 downto 0)
  );
  end MyRAM;
  
      architecture behavioral of MyRAM is
  
    constant case1:std_logic_vector(23 downto 0):= 
   (16=&gt;'1',18=&gt;'1',20=&gt;'1',22=&gt;'1',others=&gt;'0');
   constant case2:std_logic_vector(23 downto 0):= 
   (8=&gt;'1',10=&gt;'1',12=&gt;'1',14=&gt;'1',others=&gt;'0');
   constant case3:std_logic_vector(23 downto 0):= 
   (0=&gt;'1',2=&gt;'1',4=&gt;'1',6=&gt;'1',others=&gt;'0');
  
     type ram is array ( 0 to (2**ADDR_WIDTH-1)) of 
     std_logic_vector((DATA_WIDTH-1) downto 0); 
  
  
      shared variable origram:ram;
      signal s_q: std_logic_vector(23 downto 0);
  
     begin
  
      process
      begin 
  
      for ii in 1 to (2**ADDR_WIDTH-1)  loop  
      if (ii = 132) then
                   origram(ii)  := case1;
  
          elsif (ii = 133) then
                   origram(ii)  := case2;
  
          elsif (ii = 134) then   
               origram(ii)  := case3;
      else  
                  origram(ii)  :=(others=&gt;'0');           
          end if;
    end loop;
    wait;
  
   end process;   
  
  
   process (clk)
  
   begin   
      if falling_edge(clk) then
  
  
        if (we ='1') then 
           origram(to_integer(unsigned(write_addr))) := data;
           s_q &lt;= origram(to_integer(unsigned(read_addr)));
        end if;
        end if;
    end process;     
  
    q&lt;=s_q;
  end behavioral;  
  </code></pre>
  
  <p>And this is the error message:
  Error (10533): VHDL Wait Statement error at MyRAM.vhd(88): Wait Statement must contain condition clause with UNTIL keyword</p>
  
  <p>I do not have much experience in these languages, so I would appreciate  any kind of help</p>