title: VHDL multiple std_logic_vector to one large std_logic_vector
body: <p>I have four std_logic_vectors (15 downto 0) and want to stack them into a std_logic_vector (63 downt 0) so fare I have found one way of doing it but is it the correct way or is there a more optimal and correct way to do it?</p>
  
  <pre><code>signal slv16_1,slv16_2,slv16_3,slv16_4 : std_logic_vector(15 downto 0);
  signal slv64 : std_logic_vector(63 downto 0);
  
  slv64(15 downto 0) &lt;= slv16_1;
  slv64(31 downto 16) &lt;= slv16_2;
  slv64(47 downto 32) &lt;= slv16_3;
  slv64(63 downto 48) &lt;= slv16_4;
  </code></pre>