title: What's the equivalent of Verilog tilde operator "~" in VHDL?
body: <p>In Verilog and c-language, I can easy negate a vector by using the tilde operator. Example:</p>
  
  <pre><code>// Verilog
  module try;
  wire [7:0] a = 8'b1111_0000;
  reg  [7:0] b;
  
  initial begin
      b = ~a;
      // b = 8'b0000_1111;
  end
  
  endmodule
  </code></pre>
  
  <p>How would I do that same in VHDL?</p>
  
  <pre><code>-- VHDL
  library ieee;
  use ieee.std_logic_1164.all;
  
  entity design is
  end entity;
  
  architecture rtl of design is
      a: std_logic_vector(7 downto 0) := X"0F";
      b: std_logic_vector(7 downto 0);
  begin
      b &lt;= ?negate? a;
      -- result: b = X"F0"
  end architecture;
  </code></pre>