title: VHDL filtering data
body: <p>I am new to VHDL. I need to write a module to do filtering of data.  My module structure is:</p>
  
  <pre><code>a_rst - async reset
  clk - clock
  s_rst - sync reset
  valid_in - 0 - no data, 1 - where is data
  data_in - [7 downto 0]
  </code></pre>
  
  <p>Out signals:</p>
  
  <pre><code>valid_out - 0 - no data, 1 - where is data
  data_out - [7 downto 0]
  </code></pre>
  
  <p>I write testbeanch which puts to <code>data_in</code> of my module: 00,01,<b>02</b>,03,0A,02,00,01,<b>02</b>,0F.</p>
  
  <p>But my module returns: 00,01,<b>AA</b>,03,0A,02,00,01,<b>AA</b>,0F<br>
  insted of: 00,01,<b>AA</b>,03,0A,02,00,01,<b>02</b>,0F.</p>
  
  <p>I tried to do this:</p>
  
  <pre><code>--libraries
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  --entity
  entity ex6_v03 is
  port
  (
  a_rst     : in std_logic;
  clk       : in std_logic;  -- 200 MHz
  s_rst     : in std_logic;
  valid_in  : in std_logic;
  data_in   : in std_logic_vector (7 downto 0);
  valid_out : out std_logic;
  data_out  : out std_logic_vector (7 downto 0) 
  );
  end entity ex6_v03;
  
  
  architecture behavior of ex6_v03 is
  
  signal st : integer := 0;
  
  begin
  
  process(a_rst, clk)
  begin
  -- asynchronous reset
  if (a_rst = '1') then
   data_out &lt;= x"00";
   valid_out &lt;= '0';
  
  -- synchronous reset        
  elsif rising_edge(clk) then -- clk
    if (s_rst = '1') then
      valid_out &lt;= '0';
      data_out &lt;= x"00";     
    else                             
      -- normal activity
      if(valid_in = '1') then
        -- main logic
        if(data_in = x"00") then
          st &lt;= 1;
          valid_out &lt;= '1';
          data_out &lt;= data_in;
        elsif(st = 1 and data_in = x"01") then
          st &lt;= 2;
          valid_out &lt;= '1';
          data_out &lt;= data_in;
        elsif(st = 2 and data_in = x"02") then
          st &lt;= 3; 
          valid_out &lt;= '1';
          data_out &lt;= x"AA";
        elsif(st = 3 and data_in = x"03") then
          valid_out &lt;= '1';
          data_out &lt;= data_in;
          st &lt;= 0; 
        else
          st &lt;= 0;
          valid_out &lt;= '1';
          data_out &lt;= data_in;
        end if;
  
        -- end main logic
      else
        valid_out &lt;= '0';
        data_out &lt;= x"00";   
      end if; 
    end if;
  end if;
  end process;
  
  end architecture behavior;
  </code></pre>
  
  <p>But my module do not wait for 0x03 and instantly sends 0xAA.  How to fix this?</p>