title: Memory Access time in 2 level Paging
body: <p>Consider a system with a two-level paging scheme in which a regular memory
  access takes 150 nanoseconds, and servicing a page fault takes 8 ms.
  An average instruction takes 100 ns of CPU time, and two memory
  accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000
  instructions. What is the effective average instruction execution time?</p>
  
  <p>This was asked in GATE 2004. To solve the question, I would follow the below concept : <br>
  T(memory access avg) = .90(150) + .1(150+150+150) = 180 
  <em>(150- level1, 150-level2 and 150-memory)</em> <br>
  T effective = 100+ 2* 180 + 1/10000* 8* 10^6 = 1260.  <br></p>
  
  <p>Is this approach correct ? Also I have the following doubts  : <br></p>
  
  <ol>
  <li>There won't be a page fault when there is a TLB hit because the most
  frequently used pages has to be in the memory. Is it correct ? <br></li>
  <li>What is the size of the page table for a process? Say for a 32 bit
  virtual address, for every process do we allocate a page-table with
  2^32 entries ? How is the memory limits managed in paging ?</li>
  </ol>
  
  <p>Please explain theses concepts.</p>