title: How to map a single bit of a signal to multiple bits of a Vector?
body: <p>I've tried to map a bit of a signal (here <code>addS</code> of type signed(32 downto 0)) in a structural description like this:</p>
  
  <pre><code>add2 : entity work.adderSigned(behavioral) 
    generic map(N =&gt; 64)
      port map(a(63 downto 32) =&gt; mulssS, --concat 
          a(31 downto 0) =&gt; signed(muluuS), --concat
       -- b(63 downto 48) =&gt; addS(32 downto 32),
          b(63 downto 48) =&gt; (others =&gt; addS(32)), --the critical line
          b(47 downto 16) =&gt; addS(31 downto 0),
          b(15 downto 0) =&gt; (others =&gt; '0'),
          std_logic_vector(y) =&gt; y);
  </code></pre>
  
  <p>but the compiler complains that this isn't a static mapping. How can I perform this mapping?</p>