title: Instantiate Modules in Generate For Loop in Verilog
body: <p>I'm trying to instantiate some modules in Verilog using a <code>generate</code> block since I'm going to be instantiating a variable amount of them.</p>
  
  <pre><code>genvar i;
  generate
      for (i=1; i&lt;=10; i=i+1) begin
      status whatever_status (
          .clk(clk),
          .reset_n(reset_n),
          .a(a[i]),
          .b(b[i]),
          .out(out[i])
      );
  end 
  endgenerate
  </code></pre>
  
  <p><code>a</code> &amp; <code>b</code> are declared as input arrays to the parent module and <code>out</code> is declared as a array of wires.</p>
  
  <p>What am I doing wrong here?  Is this not allowed in Verilog?  Quartus is telling me:</p>
  
  <pre><code>Error (10644): Verilog HDL error at driver.v(63): this block requires a name
  </code></pre>
  
  <p>Line 63 is the for loop above.  Any help is appreciated!</p>