title: Neon VLD consuming more cycles than what is expected?
body: <p>I have a simple asm code which loads 12 quad registers of NEON, and have paralleled pairwise add instruction along with the load instruction ( to exploit the dual issue capability). I have verified the code here:</p>
  
  <p><a href="http://pulsar.webshaker.net/ccc/sample-d3a7fe78" rel="nofollow">http://pulsar.webshaker.net/ccc/sample-d3a7fe78</a></p>
  
  <p>As one can see, the code is taking around 13 cycles. But when I load the code on the board, the load instructions seems to take more than one cycle per load, I verified and found out that the VPADAL is taking 1 cycle as stated, but VLD1 is taking more than one cycle. Why is that?</p>
  
  <p>I have taken care of the following:</p>
  
  <ol>
  <li>The address is 16 byte aligned.</li>
  <li>Have provided the alignment hint in the instruction <code>vld1.64 {d0, d1} [r0,:128]!</code></li>
  <li>Tried preload instruction <code>pld [r0, #192]</code>, at places but that seems to add to the cycles instead of actually reducing the latency.</li>
  </ol>
  
  <p>Can someone tell me what am I doing wrong, why this latency?</p>
  
  <p>Other Details:</p>
  
  <ul>
  <li>With reference to cortex-a8</li>
  <li>arm-2009q1 cross compiler tool chain</li>
  <li>coding in assembly</li>
  </ul>