title: why my component doesn't work for inputs that given in vhdl
body: <p>I am new to VHDL and I have an assignment about it. I have to make a register that can save the value of Y based on the value of the last 2 bits of X. But before that, there is a process to determine Y value to be used, based on a bit of &quot;field&quot;, and this process is in the &quot;initial&quot; component. The &quot;initial&quot; component can work as expected but the &quot;Regis&quot; component, which has to save the value of Y, didn't work at all. And I don't know what's the problem, why my &quot;Regis&quot; component doesn't work as I expect. Would you help me to figure out the problem?</p>
  <p>this is my top level module vhdl :</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  entity part1 is
  Port ( X : in INTEGER;
         Y : in INTEGER;
         field : in STD_LOGIC;
         Z : out INTEGER);
  end part1;
  
  architecture Behavioral of part1 is
  component initial
  Port ( X : in INTEGER;
         Y : in INTEGER;
         FIELD : in STD_LOGIC;
         Y1 : out UNSIGNED(7 DOWNTO 0));
  end component;
  
  component regis
  Port ( y : in INTEGER;
         x : in UNSIGNED(7 DOWNTO 0);
         yout : out INTEGER);
  end component;
  
  signal yi, xr : unsigned(7 downto 0);
  signal yr, yo : integer;
  
  begin
  
  beginone : initial port map (X =&gt; X, Y =&gt; Y, FIELD =&gt; field, Y1 =&gt; yi);
  xr &lt;= to_unsigned (X, xr'length);
  yr &lt;= to_integer(unsigned(yi));
  regY : regis port map (y =&gt; yr, x =&gt; xr, yout =&gt; yo); 
  Z &lt;= yo;
  
  end Behavioral;
  </code></pre>
  <p>&quot;initial&quot; component listing :</p>
  <pre><code>signal xb, yb : unsigned(7 downto 0);
  
  begin
  xb &lt;= to_unsigned(X, xb'length);
  yb &lt;= to_unsigned(Y, yb'length);
  initial : process(FIELD, xb, by)
            variable ys : unsigned(7 downto 0);
            begin
              if (FIELD = '1') then
                 ys := yb;
                 else ys := xb xor yb;
              end if;
              Y1 &lt;= ys;
            end process;
  end Behavioral;
  </code></pre>
  <p>&quot;regis&quot; component listing :</p>
  <pre><code>begin
  process(x(1), x(0))
       begin
         if (x(1) = '0' and x(0) = '0') then yout &lt;= 0;
         elsif (x(1) = '0' and x(0) = '1') then yout &lt;= y;
         elsif (x(1) = '1' and x(0) = '0') then yout &lt;= 2*y;
         elsif (x(1) = '1' and x(0) = '1') then yout &lt;= 3*y;
         else yout &lt;= y;
         end if;
       end process;
  end Behavioral;
  </code></pre>
  <p>and this is the testbench of the top level module :</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity part1_tb is
  --  Port ( );
  end part1_tb;
  
  architecture Behavioral of part1_tb is
  component part1
  Port ( X : in INTEGER;
  Y : in INTEGER;
  field : in STD_LOGIC;
  Z : out INTEGER);
  end component;
  
  signal x, y : integer;
  signal field : std_logic;
  signal z : integer;
  
  begin
  uut : part1 port map (x =&gt; X, y =&gt; Y, field =&gt; field, z =&gt; Z);
  stim_proc : process
              begin
              wait for 100 ns;
              x &lt;= 1;
              wait for 100 ns;
              y &lt;= 2;
              wait for 100 ns;
              field &lt;= '1';
              wait;
              end process;
  end Behavioral;
  </code></pre>
  <p>if the program runs correctly, it will produce an output value of z = 2 according to the input being tested. but when the testbench simulated results z = 0.
  Thanks all.</p>
  <p><img src="https://i.stack.imgur.com/ZzAbP.png" alt="testbench simulation" /></p>