title: Multidimensional array problem in VHDL?
body: <p>I'm trying to use a multidimensional array in VHDL and I'm having a lot of trouble getting it to work properly.  My issue is that I've got an array of 17, of 16 vectors, of a given size.  What I want to do is create 17 registers that are array of 16 * std_logic_vector of 32 bits (which = my b, 512).  So, I'm trying to pass in something to input and output on the register instantiation that tells the compiler/synthesizer that I want to pass in something that is 512 bits worth...  Similar to in C if I had:</p>
  
  <pre><code>int var[COLS][ROWS][ELEMENTS];
  memcpy(&amp;var[3].. // I'm talking about 3rd COL here, passing in memory that is ROWS*ELEMENTS long
  </code></pre>
  
  <p>(My actual declaration is here:)</p>
  
  <p>type partial_pipeline_registers_type is array (0 to 16, 0 to 15) of std_logic_vector(iw - 1 downto 0);
     signal h_blk_pipelined_input : partial_pipeline_registers_type;</p>
  
  <p>I tried simply using h_blk_pipelined_input(0) .. up to (16) but this doesn't work.  I get the following error, which makes me see that I need to double index in to the array:</p>
  
  <pre><code>ERROR:HDLParsers:821 - (at the register) Wrong index type for h_blk_pipelined_input.
  </code></pre>
  
  <p>So then I tried what's below, and I get this error:</p>
  
  <pre><code>ERROR:HDLParsers:164 - (at the register code). parse error, unexpected TO, expecting COMMA or CLOSEPAR
  
  
    instantiate_h_pipelined_reg : regn
     generic map ( N=&gt; b, init =&gt; bzeros )
     port map ( clk =&gt; clk , rst =&gt; '0', en =&gt; '1',
        input =&gt; h_blk_pipelined_input((i - 1), 0 to 15),
        output=&gt; h_blk_pipelined_input((i),     0 to 15));
  -- Changing 0 to 15 to (0 to 15) has no effect...
  </code></pre>
  
  <p>I'm using XST, and from their documentation (http://www.xilinx.com/itp/xilinx6/books/data/docs/xst/xst0067_9.html), the above should have worked:</p>
  
  <pre><code>...declaration:
  
  subtype MATRIX15 is array(4 downto 0, 2 downto 0)
     of STD_LOGIC_VECTOR (7 downto 0);
  
   A multi-dimensional array signal or variable can be completely used:
  
  Just a slice of one row can be specified:
  
  MATRIX15 (4,4 downto 1) &lt;= TAB_B (3 downto 0);
  </code></pre>
  
  <p>One alternative is that I can create more  registers that are 16 times smaller, and instead of trying to do all '0 to 15' at once, I would just do that 15 additional times.  However, I think this may lead to inefficiency in synthesis and I don't feel like this is the right solution.</p>
  
  <p><strong>EDIT:</strong></p>
  
  <p>Tried what Ben said,</p>
  
  <pre><code>instantiate_h_m_qa_pipeline_registers: for i in 1 to 16 generate
  
  instantiate_h_pipelined_reg : regn
      generic map ( N=&gt; b, init =&gt; bzeros )
      port map ( clk =&gt; clk , rst =&gt; '0', en =&gt; '1',
         input =&gt; h_blk_pipelined_input(i - 1),                                            
         output=&gt; h_blk_pipelined_input(i));                                          
  end generate instantiate_h_m_qa_pipeline_registers;                                                 
  </code></pre>
  
  <p>The signals are now defined as:</p>
  
  <pre><code>type std_logic_block is array (0 to 15) of std_logic_vector(iw - 1 downto 0) ;
  type partial_pipeline_registers_type is array (0 to 16) of std_logic_block;
  signal h_blk_pipelined_input : partial_pipeline_registers_type;
  </code></pre>
  
  <p>And the error I get from XST is:</p>
  
  <p><strong>ERROR:HDLParsers:800 - ((where the register part is)) Type of input is incompatible with type of h_blk_pipelined_input.</strong></p>
  
  <p>I'm able to do everything I was able to do before, using ()() syntax instead of ( , ) so I haven't lost anything going this way, but it still doesn't resolve my problem.</p>
  
  <p><strong>EDIT:</strong></p>
  
  <p>Took it a step further and used a conversion function on the input => and output => arguments for the register instantiation, using a function to convert between the array type and just a std_logic_vector the size that I need.  It fixed the 'input => ' part, but..</p>
  
  <p><strong>Actual associated with Formal OUT mode Signal 'output' may not be a type conversion or function call. (LRM 4.3.2.2)</strong></p>