title: How to use inout and reg together in Verilog
body: <p>I have the following code:</p>
  
  <pre><code>module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4);
  // parameters
  input clock, direction, readWrite;      
  inout reg [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4;
  inout reg [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4;
  
  // code
  always @(posedge clock) begin
      if(direction==1) begin          // left to right
          assign RA1 = LA1 | LA2 | LA3 | LA4;
          assign RD1 = LD1 | LD2 | LD3 | LD4;     
          assign { RA2, RA3, RA4 } = RA1;
          assign { RD2, RD3, RD4 } = RD1;     
      end else begin
          if(direction==1) begin      // right to left
              assign LA1 = RA1 | RA2 | RA3 | RA4;
              assign LD1 = RD1 | RD2 | RD3 | RD4;     
              assign { LA2, LA3, LA4 } = LA1;
              assign { LD2, LD3, LD4 } = LD1; 
          end
      end
  end
  endmodule
  </code></pre>
  
  <p>But, on the 2nd line, the "inout reg [7:0] LD1, ..." declaration throws a syntax error in VeritakWin 3.84F. (Veritak allows "output reg" together as I have a similar code after the given code in my program). If I remove the "reg", I get the error in the assign line. If I remove "inout", I obviously get an error. I even tried removing the "assign" keywords, and also by replacing "=" with "&lt;=" , but still errors remain. What am I doing wrong? (I am new to Verilog)</p>