title: VHDL : 'X' value in result of Adder
body: <p>I have created a 4-Bit Adder , now I want to add and sub 2 registers as sign-magnitude values</p>
  
  <p>so , there is two register named A and B , two bits named As and Bs have sign bits of values in A and B , one XOR Gate for making 2-complement of B in subtraction and at the end result should store in A and As ( value and Sign ) and overflow bit in a register named AVF</p>
  
  <p>this is a simple diagram :</p>
  
  <p><img src="https://i.stack.imgur.com/v4VkO.jpg" alt="enter image description here"></p>
  
  <p>Mode = 1 => Sub; Mod = 0 => Add</p>
  
  <p>I have written this codes :</p>
  
  <p>4-Bit Adder :</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  
  ENTITY Adder_4_Bit IS
    PORT(
      A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      Mode : IN STD_LOGIC;
      Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COut : OUT STD_LOGIC
    );  
  END Adder_4_Bit;
  
  ARCHITECTURE Structure OF Adder_4_Bit IS
  COMPONENT FullAdder_1_Bit IS
    PORT(
      X, Y : IN STD_LOGIC;
      CIn  : IN STD_LOGIC;
      FSum  : OUT STD_LOGIC;
      COut : OUT STD_LOGIC
    );
  END COMPONENT;
  
  COMPONENT XORGate IS
    PORT(
      X1, X2 : IN STD_LOGIC;
      Y : OUT STD_LOGIC
    );  
  END COMPONENT;
  
  SIGNAL COut_Temp : STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL XB : STD_LOGIC_VECTOR(3 DOWNTO 0);
  
  BEGIN  
    B_0 : XORGate PORT MAP(Mode, B(0), XB(0));
    B_1 : XORGate PORT MAP(Mode, B(1), XB(1));
    B_2 : XORGate PORT MAP(Mode, B(2), XB(2));
    B_3 : XORGate PORT MAP(Mode, B(3), XB(3));
  
    SUM_0 : FullAdder_1_Bit
    PORT MAP (A(0), XB(0), Mode, Sum(0), COut_Temp(0));
  
    SUM_1 : FullAdder_1_Bit
    PORT MAP (A(1), XB(1), COut_Temp(0), Sum(1), COut_Temp(1));
  
    SUM_2 : FullAdder_1_Bit
    PORT MAP (A(2), XB(2), COut_Temp(1), Sum(2), COut_Temp(2));
  
    SUM_3 : FullAdder_1_Bit
    PORT MAP (A(3), XB(3), COut_Temp(2), Sum(3), COut);  
  END;
  </code></pre>
  
  <p>ALU :</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
  USE ieee.std_logic_unsigned.ALL;
  
  ENTITY ALU IS
    PORT(
      --Clk  : IN STD_LOGIC;
      C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      Cs : IN STD_LOGIC;
      Ds : IN STD_LOGIC;
      Mode_ALU : IN STD_LOGIC;
      Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      AVF : OUT STD_LOGIC    
    );
  END ALU;
  
  ARCHITECTURE Declare OF ALU IS
  COMPONENT Adder_4_Bit IS
    PORT(
      A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      Mode : IN STD_LOGIC;
      Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      COut : OUT STD_LOGIC
    );  
  END COMPONENT;
  
  SIGNAL E, Temp_Cs, Temp_Ds : STD_LOGIC;
  SIGNAL Temp_S : STD_LOGIC_VECTOR(3 DOWNTO 0);
  
  BEGIN   
  
   Add : Adder_4_Bit PORT MAP(C, D, Mode_ALU, Temp_S, E);   
  
  -- Sum_ALU &lt;= Temp_S;
  -- Temp_Cs &lt;= Cs;
  -- Temp_Ds &lt;= Ds;
  
   PROCESS
   BEGIN
    WAIT FOR 30 ns;
  
    Sum_ALU &lt;= Temp_S;
    Temp_Cs &lt;= Cs;
    Temp_Ds &lt;= Ds;
   END PROCESS; 
  
   PROCESS(C, D, Cs, Ds, Mode_ALU)
   BEGIN   
  
    CASE Mode_ALU IS
     WHEN '0' =&gt;
       IF ((Cs XOR Ds) = '1') THEN                                
         AVF &lt;= '0';
         IF (E = '1') THEN
           IF (Temp_S = "0000") THEN
             Temp_Cs &lt;= '0';
           END IF;
         ELSE           
           Sum_ALU &lt;= (NOT Temp_S) + "0001";
           Temp_Cs &lt;= NOT Cs;
         END IF;
       ELSE
         AVF &lt;= E;
       END IF;
  
     WHEN '1' =&gt;
       IF ((Cs XOR Ds) = '1') THEN                                  
         AVF &lt;= E;        
       ELSE       
         AVF &lt;= '0';
         IF (E = '1') THEN
           IF (Temp_S = "0000") THEN
             Temp_Cs &lt;= '0';
           END IF;
         ELSE
           Sum_ALU &lt;= (NOT Temp_S) + "0001";
           Temp_Cs &lt;= NOT Cs;
         END IF;      
       END IF;
  
     WHEN Others =&gt;  
      --   
    END CASE;
  
   END PROCESS; 
  
  END Declare;
  </code></pre>
  
  <p>Test Bench :</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
  USE ieee.std_logic_unsigned.ALL;
  
  ENTITY ALU_Test_Bench IS
  
  END ALU_Test_Bench;
  
  ARCHITECTURE Declare OF ALU_Test_Bench IS
  COMPONENT ALU IS
    PORT(
      --Clk  : IN STD_LOGIC;
      C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      Cs : IN STD_LOGIC;
      Ds : IN STD_LOGIC;
      Mode_ALU : IN STD_LOGIC;
      Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      AVF : OUT STD_LOGIC    
    ); 
  END COMPONENT;
  
  SIGNAL Xs, Ys, M, Av : STD_LOGIC;
  SIGNAL X, Y, O : STD_LOGIC_VECTOR(3 DOWNTO 0);
  
  BEGIN
  
    ALU_PM : ALU PORT MAP(X, Y, Xs, Ys, M, O, Av);
  
    Mode_Process : PROCESS
    BEGIN
    M &lt;= '1';
    WAIT FOR 10 ns;
  
    M &lt;= '0';
    WAIT FOR 10 ns;
  
    END PROCESS;
  
    Calc_Process : PROCESS
    BEGIN       
  
     X &lt;= "0010";
     Y &lt;= "1011";
     Xs &lt;= '0';
     Ys &lt;= '1';
     WAIT FOR 20 ns;
  
     X &lt;= "0110";
     Y &lt;= "0011";
     Xs &lt;= '1';
     Ys &lt;= '1'; 
     WAIT FOR 20 ns; 
  
     X &lt;= "0010";
     Y &lt;= "1011";
     Xs &lt;= '0';
     Ys &lt;= '1';
     WAIT FOR 20 ns; 
  
    END PROCESS;
  
  END Declare;
  </code></pre>
  
  <p>when I run test bench , the result value filled with 'X' :</p>
  
  <p><img src="https://i.stack.imgur.com/uepWY.jpg" alt="enter image description here"></p>
  
  <p>I know the problem is in ALU , but I can`t find the problem.</p>
  
  <p>There is no problem in 4-Bit Adder , I have tested.</p>
  
  <p>Another problem is calc sign bit of the result , Is the PROCESSes I have written correct ?</p>
  
  <p>At all what I should do to Code the diagram above ?</p>
  
  <p>thanks ...</p>