title: VHDL 32 bit ALU code
body: <p>I need to create a 32 bits ALU, with alu function, and adder/Sub, shifter, and comparator.
  when alu function is 0001, it goes to adder,
  when alu function is 0010, it goes to sub,
  when alu function is 1001, it goes to logical shifter left b-alu bits,
  when alu function is 1010, it goes to logical shifter right b-alu bits and so on.</p>
  
  <p>I already have 32 bit adder/sub and 32 bits shifter code.</p>
  
  <p>package c31L_pack is</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  package c31L_pack is
  constant ZERO          : std_logic_vector(31 downto 0) :=
    "00000000000000000000000000000000";
  constant ONES          : std_logic_vector(31 downto 0) :=
    "11111111111111111111111111111111";
  
  
  constant BW : integer:=32;
  constant SEL3   : integer:=3;
  constant SEL1   : integer:=1;
  constant OP : integer:=16;
  constant reg_field: integer:=6;
  constant immediate_size: integer:=15;
  
  
  subtype alu_function_type is std_logic_vector(3 downto 0);
  
  constant alu_nop                        : alu_function_type := "0000";
  constant alu_add                        : alu_function_type := "0001";
  constant alu_sub                        : alu_function_type := "0010";
  constant alu_comp                       : alu_function_type := "0011";
  constant alu_slt                            : alu_function_type := "0100";
  constant alu_and                        : alu_function_type := "0101";
  constant alu_or                             : alu_function_type := "0110";
  constant alu_not                        : alu_function_type := "0111";
  constant alu_xor                        : alu_function_type := "1000";
  constant alu_shift_logic_left       : alu_function_type := "1001";
  constant alu_shift_logic_right      : alu_function_type := "1010";
  constant alu_shift_arith_left       : alu_function_type := "1011";
  constant alu_shift_arith_right      : alu_function_type := "1100";
  constant alu_mov       : alu_function_type := "1101";
  
  type mux_in_16 is array((OP-1) downto 0) of std_logic_vector(BW-1 downto 0);
  type mux_in_2 is array(1 downto 0) of std_logic_vector(BW-1 downto 0);
  end;
  </code></pre>
  
  <p>1 bits:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity adder1 is
  port(a         : in  std_logic;
       b         : in  std_logic;
       cin       : in  std_logic;
       sum_def    : out std_logic;
       carry_borrow   : out std_logic);
  end; 
  
  architecture logic of adder1 is
  
  begin
  
  process(a,b,cin)
  
  begin
  
  sum_def &lt;=a xor b xor cin;
  carry_borrow&lt;=(a and b) or (a and cin) or (b and cin);
  
  end process;
  end architecture; --architecture logic
  </code></pre>
  
  <p>and 32 bits adder/sub</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use work.c31L_pack.all;
  
  entity adder32 is
  port(a3_32    : in  std_logic_vector(BW-1 downto 0);
      b3_32    : in  std_logic_vector(BW-1 downto 0);
        cin   : in std_logic;
        sub   : in std_logic;
  
        sum_32    : out std_logic_vector(BW-1 downto 0);
        cout  : inout std_logic;
        ov    : out std_logic);
  end; 
  
  architecture logic of adder32 is
  
  component adder1
  port(a         : in  std_logic;
    b         : in  std_logic;
    cin       : in  std_logic;
  
      sum_def : out std_logic;
      carry_borrow    : out std_logic);
  end component;
  
  for add1: adder1 use entity work.adder1(logic);
  
  signal carry_i :std_logic_vector(BW-2 downto 0):=(others=&gt;'0');
  signal xor_out :std_logic_vector(BW-1 downto 0):=(others=&gt;'0');
  signal oz :std_logic;
  
  begin
  
  
  Exclusive_or:for i in  BW-1 downto 0 generate
  begin
  xor_out(i)&lt;=b3_32(i) xor sub after 19ns;
  end generate;
  
  
  add1: adder1 port    map(a=&gt;a3_32(0),b=&gt;xor_out(0),cin=&gt;sub,sum_def=&gt;sum_32(0),carry_borrow=&gt;carry_i(0));   
  add_2_31 : for i in 1 to BW-2 generate
       add1 :adder1 port map(a=&gt;a3_32(i),b=&gt;xor_out(i),cin=&gt;carry_i(i-1),sum_def=&gt;sum_32(i),carry_borrow=&gt;carry_i(i)); 
  end generate;
  add32: adder1 port map(a=&gt;a3_32(BW-1),b=&gt;xor_out(BW-1),cin=&gt;carry_i(BW-2),sum_def=&gt;sum_32(BW-1),carry_borrow=&gt;cout);        
  
  oz&lt;=carry_i(BW-2) xor cout after 19 ns;
  with oz select
  ov &lt;= 'Z' when "1",
      '0' when "0";
  end architecture; --architecture logic
  </code></pre>
  
  <p>I am trying to get every result after that find out output using the function code, I got a lot of error,I try to find the way to solve that. What should I do?
  Thanks for all your help. I just want to get the add and sub first, so that I know what should I do.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use work.c31L_pack.all;
  
  ENTITY alu32 IS
  GENERIC (BW : INTEGER :=32);
  PORT ( a_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
       b_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
       alu_op : in alu_function_type ;
       g : out STD_LOGIC ;
       e : out STD_LOGIC ;
       l : out STD_LOGIC ;
       o_alu32 : out STD_LOGIC_VECTOR (BW -1 downto 0);
       c_alu32 : inout STD_LOGIC ;
       ov_alu32 : out STD_LOGIC );
  end alu32;
  
  architecture Behavioral of alu_32 is
  
  component adder32 
  port(a3_32    : in  std_logic_vector(BW-1 downto 0);-&lt;std_logic_vector&gt; is not declared.
   b3_32    : in  std_logic_vector(BW-1 downto 0);-&lt;std_logic_vector&gt; is not declared.
    cin   : in std_logic;-&lt;std_logic&gt; is not declared.
    sub   : in std_logic;-&lt;std_logic&gt; is not declared.
  
    sum_32    : out std_logic_vector(BW-1 downto 0);
    cout  : inout std_logic;
    ov    : out std_logic);
    end component;
  
  signal o1:std_logic_vector(BW-1 downto 0);
  signal c1:std_logic;
  signal ov1:std_logic;
  signal o2:std_logic_vector(BW-1 downto 0);
  signal c2:std_logic;
  signal ov2:std_logic;
  
  begin
  adder32 port map(a3_32=&gt;a_alu32,b3_32=&gt;b_alu32,cin=&gt;"0",sub=&gt;"1",sum_32=&gt;o1,cout=&gt;c1,ov=&gt;ov1);
  adder32 port map(a3_32=&gt;a_alu32,b3_32=&gt;b_alu32,cin=&gt;"0",sub=&gt;"0",sum_32=&gt;o2,cout=&gt;c2,ov=&gt;ov2);
  
  end Behavioral;
  </code></pre>
  
  <p>error massage:
  ERROR:HDLCompiler:374 Line 37: Entity  is not yet compiled.</p>
  
  <p>ERROR:HDLCompiler:69 Line 40:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 41:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 42:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 43:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 45:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 46:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 47:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 50:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 51:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 52:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 53:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 54:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:69 Line 55:  is not declared.</p>
  
  <p>ERROR:HDLCompiler:806 Line 58: Syntax error near "port".</p>
  
  <p>ERROR:HDLCompiler:806 Line 59: Syntax error near ";".</p>