title: Understanding types and subtypes vs. signals
body: <p>I currently have a bug between two version of a VHDL simulator</p>
  
  <p>my code (simple version to trigger the error)</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity test is
  end;
  
  architecture test of test is
      constant mpc_ibif_data_width          : integer := 16;
      subtype  t_mpc_ibif_data              is std_logic_vector (mpc_ibif_data_width - 1 downto 0);
  
      type t_device_2_mpc_ibif is
        record
          rd_data     : t_mpc_ibif_data;  --
          rd_data_en  : std_logic;        -- '1': rd_data must be driven to the CPU
          berr_n      : std_logic;        --
      end record;
  
      type  t_device_2_mpc_ibif_array    is array (natural range &lt;&gt;) of t_device_2_mpc_ibif;
      signal flash_cnt_2_mpc_o : t_device_2_mpc_ibif;
  begin
      process 
      begin
          wait for 10 ns;
          assert flash_cnt_2_mpc_o.rd_data = t_device_2_mpc_ibif.rd_data'(others =&gt; '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;
          wait;
      end process;
  end;
  </code></pre>
  
  <p>In the first version the following is legal</p>
  
  <pre><code>assert flash_cnt_2_mpc_o.rd_data = t_device_2_mpc_ibif.rd_data'(others =&gt; '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;
  </code></pre>
  
  <p>However in a new version, I get a "Type Error" on the same line. Specifically on </p>
  
  <pre><code>t_device_2_mpc_ibif.rd_data'(others =&gt; '0') 
  </code></pre>
  
  <p>I created this as a bug at vendor who tells me to use below code:</p>
  
  <pre><code>assert flash_cnt_2_mpc_o.rd_data = t_mpc_ibif_data'(others =&gt; '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;
  </code></pre>
  
  <p>based on these arguments</p>
  
  <blockquote>
    <p>In this context the type is expected not its selection.</p>
  </blockquote>
  
  <hr>
  
  <h3>Here is what I do not understand and want an answer to:</h3>
  
  <p>To my understanding there are types and subtypes. subtypes inherit from types</p>
  
  <p>So when you create a signal</p>
  
  <pre><code>signal NameOfSignal : std_logic_vector(1 downto 0)
  </code></pre>
  
  <p>This signal now inherit all from std_logic_vector plus its contrained IE it's a "subtype" of the type std_logic_vector.</p>
  
  <p>And regardless of the signal is in a record or not should not change this fact. </p>
  
  <p>I asked this and got the following answer:</p>
  
  <blockquote>
    <p>t_device_2_mpc_ibif.rd_data  It is not type_name neither subtype_name but selected name (element name of record).</p>
  </blockquote>
  
  <p>But in my world this shouldn't matter since the signal(element) inherit all of the types methods.</p>
  
  <p>Please correct me because I clearly misunderstand something</p>
  
  <p>EDIT: I used VHDL2008</p>
  
  <p>Regards
  Anders</p>