title: Verilog getting output as 'x' after running the test branch
body: <p>hello this my first verilog program and I am getting output value as 'x'. Can somebody please explain. Any help would be appreciated thatnks!</p>
  <pre><code>module circuit (a,b,c,d,o);
  input a,b,c,d;
  output o;
  wire e,f,g,h,i,j,k,l,m,n;
  not (a,e);
  not (b,f);
  not (g,c);
  not (d,h);
  and (i,e,g);
  and (j,e,f,c,h);
  and (k,a,f,g,h);
  and (l,a,c);
  and (m,b,g,d);
  and (n,b,c,d);
  or (o,i);
  or (o,j);
  or (o,k);
  or (o,l);
  or (o,m);
  or (o,n);
  endmodule
  module TB_circuit();    
  reg a1,b1,c1,d1;
  wire o1;
  circuit dut(.a(a1),.b(b1),.c(c1),.d(d1),.o(o1));
  initial
   begin
  a1=1;b1=0;c1=0;d1=0;#100;
  $display(o1);
  end
  endmodule
  </code></pre>