title: Interrupt handling on an SMP ARM system with a GIC
body: <p>I wanted to know how interrupt handling works from the point any device is interrupted.I know of interrupt handling in bits and pieces and would like to have clear end to end picture of interrupt handing.Let me put across what little I know about interrupt handling.</p>
  
  <p>Suppose an FPGA device is interrupted through electrical lines and get some data .Device driver for this FPGA device already had code (Interrupt handler) registered using request_irq function.</p>
  
  <p>So now  FPGA device have an IRQ line which it get after to call request_irq ,using this IRQ line device send data to the General Interrupt controller and GIC will do many to one translation of IRQ lines and send the signal to CPU core which then call below minimal code </p>
  
  <pre><code>IRQ_handler
  SUB       lr, lr, #4       ; modify LR
  SRSFD     #0x12!           ; store SPSR and LR to IRQ mode stack
  PUSH      {r0-r3, r12}     ; store AAPCS registers on to the IRQ mode stack
  BL        IRQ_handler_to_specific_device
  POP       {r0-r3, r12}     ; restore registers
  RFEFD     sp!              ; and return from the exception using pre-modified LR 
  </code></pre>
  
  <p>IRQ_handler_to_specific_device is nothing is what we registered in Device driver using request_irq() call.</p>
  
  <p>I still don't how CPU core comes to know about the interrupt source?(from which device interrupt is coming)</p>
  
  <p>Also what is role of call like do_irq and shared interrupts works?</p>
  
  <p>Need some help in understanding end to end picture on how interrupts are handled on ARM architecture?</p>