title: RISC-V Interrupt Handling Flow
body: <p>I am looking for how a RISC-V processor processes interrupt requests.</p>
  
  <p>I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title sets: the instruction set. In my view, how interrupts are handled is a question of what is called the "programmer's model" of the processor. It does not clearly fit into a document about an instruction set, because parts of interrupt processing are not expressed in instructions. Clearly, jumping into an ISR is <em>not</em> an instruction that shows up anywhere in the program code. The Instruction Set Manuals offer descriptions of say <code>mret</code> and <code>mstatus</code>, but fail to provide a holistic view.</p>
  
  <p>For a hypothetical architecture, interrupt processing might be described like this:</p>
  
  <pre><code>If the IRQ line is high and the I-bit in the status register is set,
  the processor executes the following steps atomically:
  
   - Push the PC of the next instruction onto the stack.
   - Push the status register onto the stack.
   - Clear the I-bit in the status register.
   - The PC is set to the location specified in the INTHNDLR register.
  </code></pre>
  
  <p>This is the kind of information I am looking for for the RISC-V architecture.</p>