title: Shifting 2D array Verilog
body: <p>I dont know what doesnt work on the following code, but it wont synthesize:</p>
  
  <pre><code>reg [7:0] FIFO [0:8];
  
  always@(posedge clk) begin
      if(wr &amp; !rd &amp; !full) begin
         FIFO[0:8] &lt;= {data_in, FIFO[1:8]};
      end
  end
  </code></pre>
  
  <p>I tried to index the FIFO other ways too, but nothing works. Found this topic on a Xilinx forum but I just cant figue out what he wanted to tell with that. Here is the link:</p>
  
  <p><a href="http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368" rel="noreferrer">http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368</a></p>
  
  <p>thanks </p>