title: how to delay a signal for several clock cycles in vhdl
body: <p>I'm trying to delay a signal for five clock cycles..</p>
  
  <pre><code> process (read_clk)
  begin
  if (rising_edge(read_clk)) then
      rd_delay &lt;= rd_en;
  end if;
  end process;
  
  delay3 &lt;= not(rd_en) and rd_delay;
  </code></pre>
  
  <p>By edge detecting technique,this will give me a one clock cycle delay, but i need five clock cycles.  </p>
  
  <p>Thank you all.</p>