title: Assign a synthesizable initial value to a reg in Verilog
body: <p>I'm an FPGA noob trying to learn Verilog.  How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant.  I'm trying to do something like this in the code below.  I get an error because the 8 bit constant doesn't count as input.  I also don't want to trigger the always off of a clock.  I just want to assign a register to a specific value.  As I want it to be synthesisable I can't use an initial block.  Thanks a lot. </p>
  
  <pre><code>module top
  (
      input wire clk,
      output wire [7:0] led   
   );
  
  
  reg [7:0] data_reg ; 
  always @*
  begin
      data_reg = 8'b10101011;
  end
  
  assign led = data_reg;
  
  endmodule
  </code></pre>