title: VHDL RAM 256x8 bit
body: <p>I need to write the VHDL-code for a 256x8 bit RAM. I will use bidirectional buses to manage reading and writing, but I figured I could do that using a schematic file. What I need is to create the RAM-memory as a component, but I'm struggling somewhat, since I get several code 10818 errors. Any help would be appreciated. </p>
  
  <p>The RAM memory is supposed to have one data_io port (7 downto 0 std_logic_vector), one address port (7 downto 0 std_logic_vector), as well as oe, we and clk ports (all std_logic I guess?) </p>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  ENTITY MyRAM IS 
  PORT(CLOCK,WE,OE:IN STD_LOGIC;
  ADDR:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  D_IO: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END ENTITY;
  
  ARCHITECTURE RTL OF MyRAM IS
  TYPE RAM_12 IS ARRAY (0 TO 255)OF STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAM_PTR:RAM_12;
  BEGIN
  PROCESS(CLOCK)
  BEGIN
  IF RISING_EDGE(CLOCK) THEN
  RAM_PTR(CONV_INTEGER(ADDR))&lt;=D_IO;
  ELSE 
  D_IO&lt;=RAM_PTR(CONV_INTEGER(ADDR));
  END IF;
  END PROCESS;
  END RTL;
  </code></pre>