title: compiling Verilog code in Quartus
body: <p>I'm new to verilog HDL and my first project is to implement a simple stopwatch counter using a  set of registers. I'm using Altera Quartus. </p>
  
  <p>When I tried compiling the code below, I keep getting an error for each and everyone of the registers. one of the error messages looks like this:</p>
  
  <p>Error (10028): Can't resolve multiple constant drivers for net "sec0[3]" at test_interface.v(127)</p>
  
  <p>Anyone can help? The code simulates fine in Modelsim.</p>
  
  <p>Here's the fragment of code that's causing problems:</p>
  
  <pre><code>always @ (posedge clk)
  
    if (qsoutput == 1)
        sec0 = sec0 + 1;
    else if (sec0 == 4'b1010) begin
        sec1 = sec1 + 1;
        sec0 = 4'b0000;
    end else if (sec1 == 4'b0110) begin
        min0 = min0 + 1;
        sec1 = 4'b0000;
    end else if (min0 == 4'b1010) begin
        min1 = min1 + 1;
        min0 = 4'b0000;     
    end else if (min1 == 4'b0110) begin
        sec0 = 4'b0000;
        sec1 = 4'b0000;
        min0 = 4'b0000;
        min1 = 4'b0000;
    end
  </code></pre>