title: compare and sort in VHDL
body: <p>this is a code for sorting 4 element in VHDL: </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  entity COMPARE_2 is
  PORT(
  clock   :in STD_LOGIC:='0';
  En  :in STD_LOGIC:='0';
  AA1 :buffer STD_LOGIC_VECTOR(7 DOWNTO 0);
  AA2 :buffer STD_LOGIC_VECTOR(7 DOWNTO 0);
  AA3 :buffer STD_LOGIC_VECTOR(7 DOWNTO 0);
  AA4 :buffer STD_LOGIC_VECTOR(7 DOWNTO 0);
  
  Q1  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
  Q2  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
  Q3  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
  Q4  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
  end COMPARE_2;
  
  architecture Behavioral of COMPARE_2 is
  signal  A1 : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"09";
  signal A2 : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"09";
  signal A3 : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"09";
  signal A4 : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"09";
  begin
  A1&lt;=AA1;
  A2&lt;=AA2;
  A3&lt;=AA3;
  A4&lt;=AA4;
  process(clock)
  begin
  if(clock'event and clock ='1') then
  if( En='1') then    
      if (A1 &gt;= A2 AND A1 &gt;= A3 AND A1 &gt;= A4) then    Q1 &lt;=   A1; 
      elsif (A2 &gt;= A3 AND A2 &gt;= A4 AND A2 &gt;= A1) then Q1 &lt;=   A2;
      elsif( A3 &gt;= A2 AND A3 &gt;= A4 AND A3 &gt;= A1) then Q1 &lt;=   A3;
      elsif( A4 &gt;= A3 AND A4 &gt;= A2 AND A4 &gt;= A1) then Q1 &lt;=   A4;
      end if;
  
      if ((A1 &lt;= A2 AND A1 &gt;= A3 AND A1 &gt;= A4 ) OR (A1 &gt;= A2 AND A1 &lt;= A3 AND A1 &gt;= A4) OR (A1 &gt;= A2 AND A1 &gt;= A3 AND A1 &lt;= A4) ) then    Q2 &lt;=   A1; 
      elsif ((A2 &lt;= A1 AND A2 &gt;= A3 AND A2 &gt;= A4 ) OR (A2 &gt;= A1 AND A2 &lt;= A3 AND A2 &gt;= A4) OR (A2 &gt;= A1 AND A2 &gt;= A3 AND A2 &lt;= A4)) then  Q2 &lt;=   A2; 
      elsif ((A3 &lt;= A1 AND A3 &gt;= A2 AND A3 &gt;= A4 ) OR (A3 &gt;= A1 AND A3 &lt;= A2 AND A3 &gt;= A4) OR (A3 &gt;= A1 AND A3 &gt;= A2 AND A3 &lt;= A4)) then  Q2 &lt;=   A3; 
      elsif ((A4 &lt;= A1 AND A4 &gt;= A2 AND A4 &gt;= A3 ) OR (A4 &gt;= A1 AND A4 &lt;= A2 AND A4 &gt;= A3) OR (A4 &gt;= A1 AND A4 &gt;= A2 AND A4 &lt;= A3)) then  Q2 &lt;=   A4; 
      end if;
  
      if ((A1 &lt;= A2 AND A1 &lt;= A3 AND A1 &gt;= A4 ) OR (A1 &gt;= A2 AND A1 &lt;= A3 AND A1 &lt;= A4) OR (A1 &lt;= A2 AND A1 &gt;= A3 AND A1 &lt;= A4)) then     Q3 &lt;=   A1; 
      elsif ((A2 &lt;= A1 AND A2 &lt;= A3 AND A2 &gt;= A4 ) OR (A2 &gt;= A1 AND A2 &lt;= A3 AND A2 &lt;= A4) OR (A2 &lt;= A1 AND A2 &gt;= A3 AND A2 &lt;= A4)) then  Q3 &lt;=   A2; 
      elsif ((A3 &lt;= A1 AND A3 &lt;= A2 AND A3 &gt;= A4 ) OR (A3 &gt;= A1 AND A3 &lt;= A2 AND A3 &lt;= A4) OR (A3 &lt;= A1 AND A3 &gt;= A2 AND A3 &lt;= A4)) then  Q3 &lt;=   A3;
      elsif ((A4 &lt;= A1 AND A4 &lt;= A2 AND A4 &gt;= A3 ) OR (A4 &gt;= A1 AND A4 &lt;= A2 AND A4 &lt;= A3) OR (A4 &lt;= A1 AND A4 &gt;= A2 AND A4 &lt;= A3)) then  Q3 &lt;=   A4;
      end if; 
  
      if (A1 &lt;= A2 AND A1 &lt;= A3 AND A1 &lt;= A4 )then        Q4 &lt;=   A1;
      elsif ( A2 &lt;= A3 AND A2 &lt;= A4 AND A2 &lt;= A1) then    Q4 &lt;=   A2;
      elsif( A3 &lt;= A4 AND A3 &lt;= A2 AND A3 &lt;= A1 )then     Q4 &lt;=   A3;
      elsif( A4 &lt;= A3 AND A4 &lt;= A2 AND A4 &lt;= A1 )then     Q4 &lt;=   A4;
      end if;
  end if;
  end if;
  end process;
  end Behavioral;
  </code></pre>
  
  <p>and this is another code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  
  
  entity COMPARE_2 is
      PORT(
          clock   :in STD_LOGIC;
          En  :in STD_LOGIC:='0';
          A1  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A2  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A3  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A4  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
  
          Q1  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q2  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q3  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q4  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          done    :OUT    STD_LOGIC:='0'
  
      );
  end COMPARE_2;
  
  architecture Behavioral of COMPARE_2 is
      type Com2StateMachine is (C2_start,C2_sort1,C2_sort2,C2_sort3,C2_sort4,C2_done);
      signal Com2State : Com2StateMachine:=C2_start;
  begin
      process(clock)
      begin
          if(clock'event and clock ='1') then
          c2case: case Com2State is
              when C2_start =&gt;
                  if( En='1') then    
                      Com2State &lt;= C2_sort1;
                  end if;
              when C2_sort1 =&gt;
                      if (A1 &gt;= A2 AND A1 &gt;= A3 AND A1 &gt;= A4) then    Q1 &lt;=   A1; 
                      elsif (A2 &gt;= A3 AND A2 &gt;= A4 AND A2 &gt;= A1) then Q1 &lt;=   A2;
                      elsif( A3 &gt;= A2 AND A3 &gt;= A4 AND A3 &gt;= A1) then Q1 &lt;=   A3;
                      elsif( A4 &gt;= A3 AND A4 &gt;= A2 AND A4 &gt;= A1) then Q1 &lt;=   A4;
                      end if;
                      Com2State &lt;= C2_sort2;
              when C2_sort2 =&gt;
                      if ((A1 &lt;= A2 AND A1 &gt;= A3 AND A1 &gt;= A4 ) OR (A1 &gt;= A2 AND A1 &lt;= A3 AND A1 &gt;= A4) OR (A1 &gt;= A2 AND A1 &gt;= A3 AND A1 &lt;= A4) ) then    Q2 &lt;=   A1; 
                      elsif ((A2 &lt;= A1 AND A2 &gt;= A3 AND A2 &gt;= A4 ) OR (A2 &gt;= A1 AND A2 &lt;= A3 AND A2 &gt;= A4) OR (A2 &gt;= A1 AND A2 &gt;= A3 AND A2 &lt;= A4)) then  Q2 &lt;=   A2; 
                      elsif ((A3 &lt;= A1 AND A3 &gt;= A2 AND A3 &gt;= A4 ) OR (A3 &gt;= A1 AND A3 &lt;= A2 AND A3 &gt;= A4) OR (A3 &gt;= A1 AND A3 &gt;= A2 AND A3 &lt;= A4)) then  Q2 &lt;=   A3; 
                      elsif ((A4 &lt;= A1 AND A4 &gt;= A2 AND A4 &gt;= A3 ) OR (A4 &gt;= A1 AND A4 &lt;= A2 AND A4 &gt;= A3) OR (A4 &gt;= A1 AND A4 &gt;= A2 AND A4 &lt;= A3)) then  Q2 &lt;=   A4; 
                      end if;
                      Com2State &lt;= C2_sort3;
              when C2_sort3 =&gt;
                      if ((A1 &lt;= A2 AND A1 &lt;= A3 AND A1 &gt;= A4 ) OR (A1 &gt;= A2 AND A1 &lt;= A3 AND A1 &lt;= A4) OR (A1 &lt;= A2 AND A1 &gt;= A3 AND A1 &lt;= A4)) then     Q3 &lt;=   A1; 
                      elsif ((A2 &lt;= A1 AND A2 &lt;= A3 AND A2 &gt;= A4 ) OR (A2 &gt;= A1 AND A2 &lt;= A3 AND A2 &lt;= A4) OR (A2 &lt;= A1 AND A2 &gt;= A3 AND A2 &lt;= A4)) then  Q3 &lt;=   A2; 
                      elsif ((A3 &lt;= A1 AND A3 &lt;= A2 AND A3 &gt;= A4 ) OR (A3 &gt;= A1 AND A3 &lt;= A2 AND A3 &lt;= A4) OR (A3 &lt;= A1 AND A3 &gt;= A2 AND A3 &lt;= A4)) then  Q3 &lt;=   A3;
                      elsif ((A4 &lt;= A1 AND A4 &lt;= A2 AND A4 &gt;= A3 ) OR (A4 &gt;= A1 AND A4 &lt;= A2 AND A4 &lt;= A3) OR (A4 &lt;= A1 AND A4 &gt;= A2 AND A4 &lt;= A3)) then  Q3 &lt;=   A4;
                      end if; 
                      Com2State &lt;= C2_sort4;
              when C2_sort4 =&gt;
                      if (A1 &lt;= A2 AND A1 &lt;= A3 AND A1 &lt;= A4 )then        Q4 &lt;=   A1;
                      elsif ( A2 &lt;= A3 AND A2 &lt;= A4 AND A2 &lt;= A1) then    Q4 &lt;=   A2;
                      elsif( A3 &lt;= A4 AND A3 &lt;= A2 AND A3 &lt;= A1 )then     Q4 &lt;=   A3;
                      elsif( A4 &lt;= A3 AND A4 &lt;= A2 AND A4 &lt;= A1 )then     Q4 &lt;=   A4;
                      end if;
                      Com2State &lt;= C2_done;
              when C2_done =&gt;                     
                      done&lt;='1';
                      if (En='0') then
                          Com2State &lt;= C2_start;
                      end if;
              end case c2case;
          end if;
      end process;
  end Behavioral;
  </code></pre>
  
  <p>and this is another code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  
  
  entity COMPARE_2 is
      PORT(
          clock   :in STD_LOGIC;
          En  :in STD_LOGIC:='0';
          A1  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A2  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A3  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          A4  :in STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
  
          Q1  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q2  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q3  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          Q4  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
          done    :OUT    STD_LOGIC:='0'
  
      );
  end COMPARE_2;
  
  architecture Behavioral of COMPARE_2 is
      type ArrVec4 is array (0 to 3) of std_logic_vector(7 downto 0);
  
      function sort(data :  ArrVec4) return ArrVec4 is
          variable tmp: ArrVec4;
          variable tmp2: std_logic_vector(7 downto 0);
      begin
      l0: for k in 0 to 3 loop
              tmp(k):=data(k);
          end loop l0;
      l1: for i in 0 to 2 loop
      l2:     for j in i+1 to 3 loop
                  if(tmp(i) &gt;= tmp(j)) then
                      tmp2 := tmp(j);
                      tmp(j) := tmp(i);
                      tmp(i) := tmp2;
                  end if;
              end loop l2;
          end loop l1;
          return tmp;
      end sort;
  --SIGNALS:
  
      signal i: ArrVec4;
      signal oVec : ArrVec4;
  
  
      type Com2StateMachine is (C2_start,C2_sort1,C2_sort2,C2_sort3,C2_done);
      signal Com2State : Com2StateMachine:=C2_start;
  begin
      process(clock)
      begin
          if(clock'event and clock ='1') then
          c2case: case Com2State is
              when C2_start =&gt;
                  if( En='1') then    
                      Com2State &lt;= C2_sort1;
                  end if;
              when C2_sort1 =&gt;
                      i(0) &lt;= A1;
                      i(1) &lt;= A2;
                      i(2) &lt;= A3;
                      i(3) &lt;= A4;
                      Com2State &lt;= C2_sort2;
              when C2_sort2 =&gt;
                      oVec &lt;= sort(i);
                      Com2State &lt;= C2_sort3;
              when C2_sort3 =&gt;
                      Q4 &lt;= oVec(3);
                      Q3 &lt;= oVec(2);
                      Q2 &lt;= oVec(1);
                      Q1 &lt;= oVec(0);
                      Com2State &lt;= C2_done;
              when C2_done =&gt;                     
                      done&lt;='1';
                      if (En='0') then
                          Com2State &lt;= C2_start;
                      end if;
              end case c2case;
          end if;
      end process;
  end Behavioral;
  </code></pre>
  
  <p>all of these three codes is sequential code but we know compare and sort doesn't need "clock" , I wrote another code with "WHEN" in concurrence... and all of this code work in simulation right and my clock speed in Xillinx Spartan3 is 30 MHz and ISE say that I can have 59 Mhz Clock speed for this code. it works even when I wrote a test component with using UART, but when I use this codes in my simple component about Median Filter and in large number of calculation. it doesn't work but when I use a sort code that do Sorting in 8 clock, I give answer.
  I need to mention that I instance this component in this code for use 2 , 4 byte sort for calculating median of 8 element:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  entity COMPARE_8 is
      PORT(
          clock   :IN std_logic:='0';
          en  :IN std_logic:='0';
          A1  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A2  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A3  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A4  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A5  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A6  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A7  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          A8  :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  
          Q4  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
          Q5  :OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
          done    :OUT    std_logic:='0'
      );
  end COMPARE_8;
  
  architecture Behavioral of COMPARE_8 is
      COMPONENT COMPARE_2
      PORT(
          clock : IN std_logic;
          En : IN std_logic:='0';
          A1 : in std_logic_vector(7 downto 0);
          A2 : in std_logic_vector(7 downto 0);
          A3 : in std_logic_vector(7 downto 0);
          A4 : in std_logic_vector(7 downto 0);          
          Q1 : OUT std_logic_vector(7 downto 0);
          Q2 : OUT std_logic_vector(7 downto 0);
          Q3 : OUT std_logic_vector(7 downto 0);
          Q4 : OUT std_logic_vector(7 downto 0);
          done :OUT   STD_LOGIC:='0'
          );
      END COMPONENT;
      for All: COMPARE_2 use entity WORK.COMPARE_2(Behavioral);
  
      type ComStateMachine is (C_start,C_sort,C_wait,C_done);
      signal ComState : ComStateMachine:=C_start;
      --SIGNALS:
      SIGNAL i1:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i2:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i3:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i4:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i5:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i6:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i7:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
      SIGNAL i8:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"05";
  
      SIGNAL O1:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"07";
      SIGNAL O2:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"07";
      SIGNAL O3:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
      SIGNAL O4:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
      SIGNAL O5:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
      SIGNAL O6:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
      SIGNAL O7:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
      SIGNAL O8:STD_LOGIC_VECTOR(7 DOWNTO 0):=x"06";
  
      signal enSort:STD_LOGIC:='0';
      signal doSort1:STD_LOGIC:='0';
      signal doSort2:STD_LOGIC:='0';
      signal clk:STD_LOGIC:='0';
  
  begin
      Inst1_COMPARE_2: COMPARE_2 PORT MAP(
          clock =&gt; clk,
          En =&gt; enSort,
          A1 =&gt; i1,
          A2 =&gt; i2,
          A3 =&gt; i3,
          A4 =&gt; i4,
          Q1 =&gt; O1,
          Q2 =&gt; O2,
          Q3 =&gt; O3,
          Q4 =&gt; O4,
          done =&gt; doSort1
      );
      Inst2_COMPARE_2: COMPARE_2 PORT MAP(
          clock =&gt; clk,
          En =&gt; enSort,
          A1 =&gt; i5,
          A2 =&gt; i6,
          A3 =&gt; i7,
          A4 =&gt; i8,
          Q1 =&gt; O5,
          Q2 =&gt; O6,
          Q3 =&gt; O7,
          Q4 =&gt; O8,
          done =&gt; doSort2
      );
  
      clk&lt;= clock;
      process(clock)
      begin
          if( clock'event and clock='1' ) then
          c0Case: case ComState is
              when C_start =&gt;
                  done&lt;='0';
                  if(En = '1') then
                      i1&lt;=A1;
                      i2&lt;=A2;
                      i3&lt;=A3;
                      i4&lt;=A4;
                      i5&lt;=A5;
                      i6&lt;=A6;
                      i7&lt;=A7;
                      i8&lt;=A8;
  --                  i1&lt;=x"09";
  --                  i2&lt;=x"02";
  --                  i3&lt;=x"03";
  --                  i4&lt;=x"06";
  --                  i5&lt;=x"2b";
  --                  i6&lt;=x"1a";
  --                  i7&lt;=x"0c";
  --                  i8&lt;=x"01";
                      ComState &lt;= C_sort;
                  end if;
              when C_sort =&gt;
                  enSort&lt;='1';
                  ComState &lt;= C_wait;
              when C_wait =&gt;
                  if(doSort1='1' and doSort2='1') then
                      enSort&lt;='0';
                      if( O5 &lt;= O4 ) then
                          Q4 &lt;= O4;
                          Q5 &lt;= O5;
                      end if;
                      if( O6 &lt;= O3 AND O6 &gt;= O4 ) then 
                          Q5 &lt;= O6;
                      end if;
                      if( O7 &lt;= O2 AND O7 &gt;= O3) then
                          Q5 &lt;= O7;
                      end if;
                      if( O8 &lt;= O1 AND O8 &gt;= O2)then 
                          Q5 &lt;=O8;
                      end if;
  
                      if(O1 &lt;= O8 )then
                          Q5 &lt;= O1;
                      end if;
                      if( O2 &lt;= O7 AND O2 &gt;= O8)then
                          Q5 &lt;=O2;
                      end if;
                      if( O3 &lt;= O6 AND O3 &gt;= O7)then
                          Q5 &lt;=O3;
                      end if;
                      if(O4 &lt;= O5 AND O4 &gt;= O6)then
                          Q5 &lt;=O4 ;
                      end if;
  
                      if( O5 &lt;= O3 AND O5 &gt;= O4) then
                          Q4 &lt;= O5;
                      end if;
                      if( O6 &lt;= O2 AND O6 &gt;= O3)then
                          Q4 &lt;= O6;
                      end if;
                      if(O7 &lt;= O1 AND O7 &gt;= O2 )then
                          Q4 &lt;= O7;
                      end if;
                      if( O8 &gt;= O1) then
                          Q4 &lt;= O8;
                      end if;
                      if( O1 &lt;= O7 AND O1 &gt;= O8 )then
                          Q4 &lt;= O1;
                      end if;
                      if( O2 &lt;= O6 AND O2 &gt;= O7) then
                          Q4 &lt;= O2;
                      end if;
                      if(O3 &lt;= O5 AND O3 &gt;= O6)then
                          Q4 &lt;= O3;
                      end if;
  --                  if(O3 &lt;= O7 AND O3 &gt;= O8)then
  --                      Q4 &lt;= O4;
  --                  end if;
                      ComState &lt;= C_done;
                  end if;
              when C_done =&gt;
                  done&lt;='1';
                  if(En='0')then
                      ComState &lt;= C_start;
                  end if;
              end case c0Case;
          end if;
      end process;
  end Behavioral;
  </code></pre>
  
  <p>now I don't know why I can't use concurrence sorting with "when" and all of this codes run fine in simulation and can run maximum 59 Mhz and I have 30 Mhz clock?</p>
  
  <p>"I gave that random default values for debugging my code" </p>