title: System Verilog: Casting from logic to int
body: <p>I am trying to cast a 'logic [2:0]' type to an integer in system verilog. It took me awhile to realize this was the problem why my test was not working as expected.</p>
  
  <p>I was trying to cast it like this:</p>
  
  <pre><code>int a = int '(signal);
  </code></pre>
  
  <p>Where signal is a logic [2:0]. But this was always assigning a as 0.</p>
  
  <p>Currently this code:</p>
  
  <pre><code>     int a;
       if(signal=== 3'b000) begin
          a = 0;
       end else if(signal=== 3'b001) begin
          a = 1;
       end else if(signal=== 3'b010) begin
          a = 2;
       end else if(signal=== 3'b011) begin
          a = 3;
       end else begin
          assert(0);
       end
  </code></pre>
  
  <p>works but I would really like to be able to cast this type.</p>
  
  <p>I really could not find this addressed in ANY sites, book, or stackoverflow thread so if someone finds a duplicate I will be thoroughly embarrassed</p>