title: DMA Transfer Data Rate
body: <p>I'm trying to learn about DMA transfer rates and I don't understand this questions. I have the answers but don't know how to get there.</p>
  
  <p>This question concerns the use of DMA to handle the input and storage in memory of data arriving at an input interface, the achievable data rates that can achieved using this mechanism, and the bus bandwidth (capacity) used for particular data rates.
  You are given details of the execution of the clock cycles executed for each DMA transfer, and the clock cycles to acquire and release the busses.
  Below you are given: the number of clock cycles required for the DMA device to transfer a single data item between the input interface and memory, the number of clock cycles to acquire and releases the system busses, the size (in bits) of each data item, and the clock frequency.</p>
  
  <p>number of clock cycles for each data transfer 8</p>
  
  <p>number of clock cycles to acquire and release busses 4</p>
  
  <p>number of bits per data item = 8</p>
  
  <p>clock frequency = 20MHz</p>
  
  <p>A) What is the maximum achievable data rate in Kbits/second?</p>
  
  <p>B) What percentage of the bus clocks are used by the DMA device if the data rate is 267Kbits/sec?</p>
  
  <p>Answers</p>
  
  <p>A)20000.0</p>
  
  <p>B)2.0</p>
  
  <p>Thanks in advance. </p>