title: same source, different clk frequency(multi-clock design)
body: <p>how to handle the multi-clock design signals with the clock generated from the same source?
  For example, 
  one clock domain is 25Mhz
  the other one is 100Mhz
  how can I handle the data bus from 25Mhz to 100Mhz
  and also 100Mhz to 25Hhz?</p>
  
  <p>don't want to use AFIFO tho
  any other easy CDC way to handle it?</p>