title: verilog code of FIFO (first in first out) is not showing the proper result?
body: <p>I wanted to design a FIFO having a certain depth and width.  The Verilog code of the FIFO is written in Vivado 2017.4.  The code is able to to read the input data, but it is only showing XX as the output. The design sources and test bench of the FIFO is given below. Help me to find the problem.</p>
  
  <pre><code>module fifo #(parameter WIDTH=8, parameter DEPTH=8) (
      input wire [WIDTH-1:0] data_in,
      output reg [WIDTH-1:0] data_out,
          output reg data_valid,
          input wire reset,
      input wire clk
      );
          function integer clog2(input reg [32-1:0] value); 
          begin 
              value = value-1;
              for (clog2=0; value&gt;0; clog2=clog2+1)
                  value = value&gt;&gt;1;
          end 
      endfunction
          reg [WIDTH-1:0] data [DEPTH-1:0];
      reg [clog2(DEPTH)-1:0] write_pointer;
      reg [clog2(DEPTH)-1:0] read_pointer;
          always @(posedge clk) begin
          if (reset == 1'b0) begin
              write_pointer &lt;= 0;
              read_pointer &lt;= 1;
              data_valid &lt;= 0;
          end else begin
              if (write_pointer == DEPTH-1) write_pointer &lt;= 0;
              else write_pointer &lt;= write_pointer + 1;
                  if (read_pointer == DEPTH-1) read_pointer &lt;= 0;
              else read_pointer &lt;= read_pointer + 1;
                  data[write_pointer] &lt;= data_in;
              data_out &lt;= data[read_pointer];
          end
              if (read_pointer == 0) data_valid &lt;= 1'b1;
      end
      endmodule
  </code></pre>
  
  <h2>test bench</h2>
  
  <pre><code>`timescale 1ns / 1ps
  module fifo_tb;
      parameter WIDTH = 16;
      parameter DEPTH = 8;
      reg reset;
      reg clk;
  reg [(WIDTH-1):0] data_in;
      wire [(WIDTH-1):0] data_out;
      wire data_valid;    
     fifo #(WIDTH,DEPTH) U0(data_in,data_out,data_valid,reset,clk);
       initial begin
          clk = 0;
          reset = 1;
          #1 reset = 0;
          #1 reset = 1;
  
      end
  
      // Create clock
      always
      #5 clk = ~clk;
  
  reg signed [15:0] rom_memory [4096-1:0];
  integer i=0;
  initial 
  begin
      $readmemh("C:\\Users\\input_7_zz.txt",rom_memory);
  
  end
  
  always@(posedge clk )
  begin
      if(~reset)
      begin
      data_in &lt;= 0;
      end
      else
      begin
        data_in &lt;= rom_memory[i];
       i &lt;= i+ 1;
   end
  
  end
  endmodule
  </code></pre>