title: Is there ever a reason for "? 1 : 0" in Verilog?
body: <p><em>Computer Organization and Design</em> (5th edition) by Hennessy and Patterson includes this Verilog code in Figure B.5.15 (p. B-37):</p>
  
  <pre><code>ALUOut &lt;= A &lt; B ? 1:0;
  </code></pre>
  
  <p>Is there any reason not to write this simpler statement instead:</p>
  
  <pre><code>ALUOut &lt;= A &lt; B;
  </code></pre>
  
  <p>In general, is there ever a reason to write "? 1 : 0" in Verilog?</p>