title: How do I convert a number to two's complement in verilog?
body: <p>I am trying to design a 4-bit adder subtracter in verilog. This is only the second thing I have ever written in verilog, and I don't know all the correct syntax yet. This is the module I have so far:</p>
  
  <pre><code>module Question3(carryin, X, Y, Z, S, carryout, overflow);
      parameter n = 4;
      input carryin, Z;
      input [n-1:0]X, Y;
      output reg [n-1:0]S;
      output reg carryout, overflow;
  
      if(Z==0)
      begin
          Y = not(y) + 4'b0001;
      end
  
      always @(X, Y, carryin)
          begin
              {carryout, S} = X + Y + carryin;
              overflow = carryout ^ X[n-1]^Y[n-1]^S[n-1];
          end
  
  endmodule
  </code></pre>
  
  <p>My compiler (xilinx 10.1), keeps saying "Syntax error near if." I have tried many different ways of doing the conversion, including just using a Case that takes Y as an argument, then checks all the possible 4-bit combinations, and converts them to two's complement.</p>
  
  <p>Z is what determines if the adder does subtraction or addition. If it's 0, it means subtraction, and I want to convert y to two's complement, then just do regular addition. I'm sure the rest of the adder is correct, I just do not know what is wrong with the part where I'm trying to convert.</p>