title: using circular memory to make the 1 second sound delay in verilog
body: <pre><code>module delay(
  input [11:0] data_in,
  input delay_clk,    //here i will use a 20kHz clk
  output reg [11:0] data_out
      );
  
      reg[11:0]memory[0:20000];
      reg[15:0]write_index;//i
      reg[15:0]read_index;//j
  
  
      initial begin
        write_index = 16'b0000000000000000;
        read_index = 16'b0100111000100000;
      end
  
  
      always@(posedge delay_clk) begin
         read_index = read_index+1;    
         memory [write_index] &lt;= data_in;
         data_out &lt;= memory[read_index];   
      end
  
  endmodule
  </code></pre>
  
  <p>I want to make a 1 second delay by using the circular memory.
  I generate bitstream and program it to FGPA but there is no sound come out.
  So how can i improve this verilog codes?</p>