title: PRBS Generator module in VHDL
body: <p>Here i am posting a snapshot of prbs</p>
  
  <p>My code for prbs module is </p>
  
  <pre><code>-- Module Name:    prbs - Behavioral 
  -- Project Name:   modulator
  
  -- Description: 
  --To make it of N bit replace existing value of N with desired value of N
  ----------------------------------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  ---- Uncomment the following library declaration if instantiating
  ---- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity prbs is
      Port ( pclock : in  STD_LOGIC;
              preset : IN std_logic := '0';
             prbsout : out  STD_LOGIC);
  end prbs;
  
  architecture Behavioral of prbs is
  
  COMPONENT dff is
      PORT(
          dclock : IN std_logic;
          dreset : IN std_logic;
          din : IN std_logic ;          
          dout : OUT std_logic 
          );
      END COMPONENT;
  
  
  signal dintern : std_logic_vector (4 downto 1); --Change value of N to change size of shift register
  signal feedback : std_logic := '0';
  
  begin
  
  instdff : dff port map (pclock , preset , feedback , dintern(1));
  genreg : for i in 2 to 4 generate --Change Value of N Here to generate that many instance of d flip flop
  begin
  instdff : dff port map ( pclock , preset , dintern(i-1) , dintern(i));
  end generate genreg;
  
  main : process(pclock)
  
  begin
      if pclock'event and pclock = '1' then   
              if preset = '0'  then
                  if dintern /= "0" then
  
                      feedback &lt;= dintern(1) xor dintern(3); -- For N equals four;
                      --feedback &lt;= dintern(4) xor dintern(5) xor dintern(6) xor dintern(8); -- For N equals eight;
                      --feedback &lt;= dintern(11) xor dintern(13) xor dintern(14) xor dintern(16); -- For N equals sixteen;
                      --feedback &lt;= dintern(1) xor dintern(2) xor dintern(22) xor dintern(32); -- For N equals thirty two                     
  
                  else
                  feedback &lt;= '1';
                  end if;
              end if;                                     
      end if; 
  end process main;
  
  prbsout &lt;= dintern(4) ; --Change Value of N Here to take output to top entity 
  
  end Behavioral;
  </code></pre>
  
  <p>In it i am instantiating a d flip flop module</p>
  
  <p>d ff module code </p>
  
  <pre><code>----------------------------------------------------------------------------------
  -- Module Name:    dff - Behavioral 
  -- Project Name: 
  -- Description: 
  ----------------------------------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  ---- Uncomment the following library declaration if instantiating
  ---- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  entity dff is
      Port ( dclock : in  STD_LOGIC ;
             dreset : in  STD_LOGIC ;
             din : in  STD_LOGIC;
             dout : out  STD_LOGIC);
  end dff;
  
  architecture Behavioral of dff is
  
  begin
  process(dclock)
  
  begin
      if dclock'event and dclock = '1' then
          if dreset = '0' then
              dout &lt;= din;
        else
              dout &lt;= '1';
          end if;
      end if;
  end process;
  
  
  end Behavioral;
  </code></pre>
  
  <p>But i am not getting desired output.
  In top level entity i am getting always 1 at prbsout signal.</p>
  
  <p>When i try to simulate then prbsout signal becomes undefined.</p>
  
  <p>What i am missing?</p>