title: Target (variable "") is not a signal error in VHDL
body: <p>I have this piece of code </p>
  
  <pre><code>  function func (k1, k2 : in bit_vector) return bit_vector is
  
      variable result : bit_vector(1 to 32);
  
      begin
          for i in 0 to 31 loop
              result(i) &lt;= k1(i);
          end loop;
  
          return result;
      end func;
  </code></pre>
  
  <p>I get this error : </p>
  
  <blockquote>
    <p>target (variable "result") is not a signal</p>
  </blockquote>
  
  <p>I know I need to change the type of result but I don't know what it should be.
  Thanks.</p>