title: stm32 NVIC_EnableIRQ() bare metal equivalent?
body: <p>I'm using the blue pill, and trying to figure out interrupts. I have an interrupt handler:</p>
  <pre><code>void __attribute__ ((interrupt (&quot;TIM4_IRQHandler&quot;))) myhandler()
  {
      puts(&quot;hi&quot;);
      TIM4-&gt;EGR |= TIM_EGR_UG; // send an update even to reset timer and apply settings
      TIM4-&gt;SR &amp;= ~0x01; // clear UIF
      TIM4-&gt;DIER |= 0x01; // UIE
  }
  </code></pre>
  <p>I set up the timer:</p>
  <pre><code>    RCC_APB1ENR |= RCC_APB1ENR_TIM4EN;
      TIM4-&gt;PSC=7999;
      TIM4-&gt;ARR=1000;
      TIM4-&gt;EGR |= TIM_EGR_UG; // send an update even to reset timer and apply settings
      TIM4-&gt;EGR |= (TIM_EGR_TG | TIM_EGR_UG);
      TIM4-&gt;DIER |= 0x01; // UIE enable interrupt
      TIM4-&gt;CR1 |= TIM_CR1_CEN;
     
  </code></pre>
  <p>My timer doesn't seem to activate. I don't think I've actually enabled it though. Have I??</p>
  <p>I see in lots of example code commands like:</p>
  <pre><code>NVIC_EnableIRQ(USART1_IRQn);
  </code></pre>
  <p>What is actually going in NVIC_EnableIRQ()?</p>
  <p>I've googled around, but I can't find actual bare-metal code that's doing something similar to mine.</p>
  <p>I seem to be missing a crucial step.</p>
  <p><strong>Update 2020-09-23</strong> Thanks to the respondents to this question. The trick is to set the bit for the interrupt number in an NVIC_ISER register. As I pointed out below, this doesn't seem to be mentioned in the STM32F101xx reference manual, so I probably would never have been able to figure this out on my own; not that I have any real skill in reading datasheets.</p>
  <p>Anyway, oh joy, I managed to get interrupts working! You can see the code here: <a href="https://github.com/blippy/rpi/tree/master/stm32/bare/04-timer-interrupt" rel="nofollow noreferrer">https://github.com/blippy/rpi/tree/master/stm32/bare/04-timer-interrupt</a></p>