title: Using FOR loop in VHDL with a variable
body: <p>Is there any possible way to create a for loop in the form:</p>
  
  <pre><code>for i in 0 to some_var loop
      // blah,blah
  end loop;
  </code></pre>
  
  <p>If not, is there any alternative way to create the same loop? Since While loops allows to use variable as the limit, but they are not synthesizeable in my project.</p>
  
  <p>Thanks in Advance,</p>
  
  <p>Bojan Matovski</p>