title: system verilog assertion disable condition
body: <p>I have this assertion in order to check clk freq: </p>
  
  <pre><code>assert property clk_freq;
  int cnt;
  @(posedge fast_clk, clk_1MHz) disable_iff(!enable_check)
  ($rose(clk_1MHz), cnt=0) |=&gt; (!$rose(clk_1MHz),cnt++) [*0:$] ##1 $rose(clk_1MHz), cnt==fast_clk_freq;
  endproperty
  </code></pre>
  
  <p>fast_clk starts to toggle during (not from beginning) of the simulation after disable_check is asserted.
  The problem is that it seems that the assertion ignores the <code>disable_iff</code>
  Question: is a $rose(clk_1Mhz) event "registered" even though the assertion is disabled (or am I missing something else ?) </p>