title: Verilog error: Range must be bounded by constant expressions
body: <p>I'm new to verilog and I am doing a project for my class. So here is my code:  </p>
  
  <pre><code>wire [n-1:0] subcounter_of_counter;
  reg [n-1:0] mask,free;
  //subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id)
  always @(*) begin //command or id or mask or free or subcounter_of_counter
  if (command==increment) begin
      for (int i = 0; i &lt; n; i=i+1)begin
          if (i&lt;id) begin
              subcounter_of_counter[i]=1'b0;
          end else if (i==id) begin
              subcounter_of_counter[i]=1'b1;
          end else begin
              if( (|mask[id+1:i]) || (|free[id+1:i]) ) begin
                  subcounter_of_counter[i]=1'b0;
              end else begin
                  subcounter_of_counter[i]=1'b1;
              end
          end
      end
  end
  end
  </code></pre>
  
  <p>And the error says <em>"the range must be bounded by constant expressions."</em>   </p>
  
  <p>Any ideas how else I could write it to do the same operation?  </p>
  
  <p>Thanks a lot</p>