title: Verilog - Port Size Does Not Match Connection Size
body: <p>Using ModelSim PE Student Edition 10.4a. Wrote a module for a 1-4 demux. Wrote a test bench for that module. Compiles fine. When trying to simulate, I get the following errors:</p>
  
  <blockquote>
    <p># ** Warning: (vsim-3015) D:/ModelSim/examples/Lab3_3.v(42): [PCDPC] - Port size (1) does not match connection size (4) for port 'in'. The port definition is at: D:/ModelSim/examples/Lab3_3.v(1).<br>
    #    Time: 0 ns  Iteration: 0  Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v<br>
    # ** Error (suppressible): (vsim-3053) D:/ModelSim/examples/Lab3_3.v(42): Illegal output or inout port connection for port 'out'.
    #    Time: 0 ns  Iteration: 0  Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v<br>
    # ** Warning: (vsim-3015) D:/ModelSim/examples/Lab3_3.v(42): [PCDPC] - Port size (4) does not match connection size (1) for port 'out'. The port definition is at: D:/ModelSim/examples/Lab3_3.v(1).<br>
    #    Time: 0 ns  Iteration: 0  Instance: /tb_demux/DA0 File: D:/ModelSim/examples/Lab3_3.v</p>
  </blockquote>
  
  <p>Code is:</p>
  
  <pre><code>module demux(input in, input[1:0] S, output reg[3:0] out);
  
  
  always @(in or S)
  begin
       case(S)
      2'b00: begin
          out[0] = in;
          out[1] = 0;
          out[2] = 0;
          out[3] = 0;
          end
      2'b01: begin
          out[0] = 0;
          out[1] = in;
          out[2] = 0;
          out[3] = 0;
          end
      2'b10: begin
          out[0] = 0;
          out[1] = 0;
          out[2] = in;
          out[3] = 0;
          end
      2'b11: begin
          out[0] = 0;
          out[1] = 0;
          out[2] = 0;
          out[3] = in;
          end
       endcase
  end
  
  endmodule   
  
  
  module tb_demux;
  wire[3:0] out;
  reg[1:0] S;
  reg in;
  
  demux DA0(out, S, in);
  
  initial
  begin
  
      S = 2'b00; in = 0;
      #100 S = 2'b01; in = 1;
      #100 S = 2'b10; in = 0;
      #100 S = 2'b11; in = 1;
  end
  
  initial #400 $stop;
  
  initial $monitor("Select = %b, In = %b, Out = %b", S, in, out);
  endmodule
  </code></pre>
  
  <p>Cannot seem to make this work.  Thanks.</p>