title: Task to measure clock frequency in System Verilog (pass clock signal by reference)
body: <p>I'm new to SV for verification and as a first attempt to a object oriented testbench, I'm trying to verify a simple clock generator design.
  I would like to constantly monitor the multple clock outputs of the macro, given a certain configuration and clock input. To do so I need to be able to measure the frequency of multiple clock signals.</p>
  <p>Ideally, I thought of something like this for my <code>checker</code> class:</p>
  <ul>
  <li>get trigger and retrieve configuration details</li>
  <li>start a <code>freq_meter</code> task for each output clock I need to measure</li>
  </ul>
  <p>Each <code>freq_meter</code> task would do the following:</p>
  <ul>
  <li><strong>receive a clk signal from the virtual interface</strong></li>
  <li>start time measure</li>
  <li>count N clock posedges</li>
  <li>return the evaluated frequency</li>
  </ul>
  <pre><code>class checker_monitor;
    virtual clkgen_if clkgen_vif;
  
    task run();
      // launch freq measure
      fork
        freq_meter(clkgen_vif.clk_out_1);
        freq_meter(clkgen_vif.clk_out_2);
        freq_meter(clkgen_vif.clk_out_3);
      join
      // check that returned frequencies are correct
    endtask
  
    task freq_meter(input logic clk, output logic freq);
      time_start = $time;
      repeat(N+1) @ (posedge clk);
      time_end = $time;
  
      period = (time_end - time_start)/N;
      freq = 1/period;
    endtask : freq_meter
  </code></pre>
  <p>Any suggestions on such a problem? I'm stuck now at passing a clock signal by reference to the task from the virtual interface.</p>
  <p>Best,</p>
  <p>abet</p>