title: How can I debug my verilog code for concatenating the MSB to LSB of 2 4bit number?
body: <p>It complains <code>Input a&lt;2:0&gt;</code> and <code>Input b&lt;2:0&gt;</code> is never used .The output is just displaying the concatenation of <code>a[3]</code> and <code>b[3]</code> (<code>a = 1001</code>, <code>b = 1100</code>).</p>
  
  <pre><code>module stone(a,b,rslt);
    input      [3:0] a,b;
    output reg [0:1] rslt;
    integer i;
    always @(a,b)
    begin
      for (i = 0; i &lt;= 3; i = i + 1)
        rslt =  {a[i],b[i]};
    end
  endmodule
  </code></pre>