title: Delay output signal for 3 clock cycles in VHDL
body: <p>If the reset signal is '0' then "EN" goes high and "clr" goes low. However, if the reset signal goes high on the rising edge of the clock then "EN" goes low and "clr" goes high. I accomplished this in my code, but i need to delay the output signal produced when reset goes high[ EN = 0/ CLR = 1] for 3 more clock cycles. I tried using a counter, but it produced the same answer.</p>
  
  <pre><code>BEGIN
      process ( Reset, Clk)
      begin
          if Reset = '0' then
                  En &lt;= '1';
                  clr &lt;= '0';
          elsif rising_edge(Clk) then
              if Reset = '1' then
                  En &lt;= '0';
                  clr &lt;= '1';
              end if;
          end if;
      end process;
  
  END description;   
  </code></pre>