title: Connecting STD_LOGIC_VECTOR in different ways (Barrel Shifter) - VHDL
body: <p>I am realizing a N-bit Barrel Shifter.</p>
  
  <p>Here it is my component:</p>
  
  <pre><code>entity barrel_shifter is
      Generic ( N : integer := 4);
      Port ( data_in : in  STD_LOGIC_VECTOR (N-1 downto 0);
             shift : in  STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N =&gt; number of inputs for the shift
             data_out : out  STD_LOGIC_VECTOR (N-1 downto 0));
  end barrel_shifter;
  </code></pre>
  
  <p>For my purpose I've created an N-bit multiplexer too, and this is its code:</p>
  
  <pre><code>entity mux is
      Generic ( N : integer := 4);
      Port ( data_in : in  STD_LOGIC_VECTOR (N-1 downto 0);
             sel : in  STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N =&gt; number of inputs for the shift
             data_out : out  STD_LOGIC);
  end mux;
  
  architecture Behavioral of mux is
  
  begin
      data_out &lt;= data_in(to_integer(unsigned(sel)));
  end Behavioral;
  </code></pre>
  
  <p>Now to realize a Circular Barrel Shifter I need to connect these N multiplexer in different ways. You can find an example <a href="http://www.xilinx.com/support/documentation/application_notes/xapp195.pdf" rel="nofollow" title="PDF">here</a>, page 2, figure 1. As you can see IN0 is connected only one time to the D0 multiplexer input. The next time IN0 is connected to the D1 multiplexer input, and so on... (it's the same logic for the other inputs)</p>
  
  <p>But how can I realize in VHDL something like that? If I hadn't STD_LOGIC_VECTOR as input it would be easy, but I need to make a generic Barrel Shifter (with generic map construct), so I can't manually connect each wire because I don't know the value of the generic N.</p>
  
  <p>In my barrel_shifter entity I tried this:</p>
  
  <pre><code>architecture Structural of barrel_shifter is
  
      signal q : STD_LOGIC_VECTOR (N-1 downto 0);
  
  begin
  
      connections: for i in 0 to N-1 generate
          mux: entity work.mux(Behavioral) generic map(N) port map(std_logic_vector(unsigned(data_in) srl 1), shift, q(i));
      end generate connections;
  
      data_out &lt;= q;
  
  end Structural;
  </code></pre>
  
  <p>But it simply doesn't work ("Actual, result of operator, associated with Formal Signal, Signal 'data_in', is not a Signal. (LRM 2.1.1)"). I've tried using variable and signals, like this:</p>
  
  <pre><code>data_tmp := data_in(i downto 0) &amp; data_in(N-i downto 1);
  </code></pre>
  
  <p>But I still couldn't figure out the right way to do these connections.</p>