title: Always block instead of assign, simulated in FPGA
body: <p>I am trying to code and synthesize in Verilog. Sometimes I am still getting confused with using Verilog as a typical C like programming language, I am trying to understand if there will be a difference between 2 different codes:</p>
  
  <pre><code>always @ (a1,a0,b1,b0)
  begin
  case ({a1,a0,b1,b0})
                   4'b0000 : s= 7'b1110111 ;
                   4'b0001 : s= 7'b1110111  ;
                    ....
                    ....
                   4'b1110 : s= 7'b0101111  ; 
                   4'b1111 : s= 7'b1111010 ;
                   endcase
  
  
      end      
  </code></pre>
  
  <p>and</p>
  
  <p>using the above code logic with assign, instead of always block.</p>
  
  <p>Will the above code generate a latch? In which case would it generate a latch? Will there be any delay difference between using the 2 codes?</p>
  
  <p>PS we are trying to create a 2bit binary multiplier, which outputs to a 7 segm display.
  Thank you.</p>