title: Compile multiple Kernel modules that share code
body: <p>I whish to compile two Kernel modules (out of tree) that share a common library : module1.c uses functions from library.c and module2.c also uses functions from library.c. But, library.c implements a global variable "my_variable" that need to be shared between module1.c and module2.c.</p>
  
  <p>For now, I have the following Makefile : </p>
  
  <pre><code># List of files
  obj-m   += my_module1.o my_module2.o
  
  my_module1-objs := library.o module1.o
  my_module2-objs := library.o module2.o
  
  all:    
      make -C $(KERNEL_DIR) M=$(PWD) modules
  </code></pre>
  
  <p>$(KERNEL_DIR) and $(PWD) are set before makefile is called.</p>
  
  <p>That makefile makes the following output :</p>
  
  <pre><code>CC library.o
  CC module1.o
  LD my_module1.o
  CC library.o
  CC module2.o
  LD my_module2.o
  CC my_module1.mod.o
  LD my_module1.ko
  CC my_module2.mod.o
  LD my_module2.ko
  </code></pre>
  
  <p>library.c is compiled twice, for each module that uses it. So there is two different "my_variables" objects that live independently, thing that I want to avoid.</p>
  
  <p>How can I modify the Makefile to first, compile library.c => library.o then use the same library.o to compile each Kernel modules ?</p>
  
  <p>Thanks a lot.</p>