title: System Verilog - forcing a signal to invert / flip
body: <p>Is forcing a signal's bit to flip using this method valid ?</p>
  
  <p>1.</p>
  
  <pre><code>task
  begin
  force higher_level.lower_level.a[1] = ~higher_level.lower_level.a[1];
  end 
  </code></pre>
  
  <p>I've tried this with mixed results at best. Sometimes the bit flips, while sometimes it remains the the same.</p>
  
  <p>However, I've also written a less elegant code with for the same purpose of flipping the bits, which works all the time, as seen below:</p>
  
  <p>2.</p>
  
  <pre><code>task
  begin
  if(higher_level.lower_level.a[1] == 1'b1)
  force higher_level.lower_level.a[1] = 1'b0;
  else
  force higher_level.lower_level.a[1] = 1'b1;
  end
  </code></pre>
  
  <p>Is the first code not good way of flipping the bits? Or is there something else I'm missing out? </p>
  
  <p>Where<code>higher_level.lower_level.a[51:0]</code> is a 52-bit signal </p>
  
  <p>Thanks :D</p>