title: Makefile wildcard rules for multiple file extensions
body: <p>I have a number of assembly and C source files in a directory. I have mentioned a list of files to be compiled as <code>C_OBJFILES</code> and <code>ASM_OBJFILES</code>. I have added the rules as</p>
  
  <pre><code>%.o: %.S
      $(AS) $(ASFLAGS) -o $@ $&lt;
  
  %.o: %.c
      $(CC) $(CFLAGS) -o $@ $&lt;
  </code></pre>
  
  <p>for generating the object files. Some of the assembly files has .s extension. Some has .S and remaining .asm. Is there a way to specify these different extensions in a single rule instead of separate %.o:%.asm and %.o:%.s?</p>
  
  <p>Although it can be solved by a simple prename before make, I would like to explore the options with Makefile. Below is the complete Makefile I have written.</p>
  
  <pre><code>ASM_OBJLIST:=startup.o vectors.o lowlevel.o
  C_OBJLIST:=test.o
  LD_SCRIPT:=test.ld
  
  CROSS_COMPILE:=arm-none-eabi-
  AS:=$(CROSS_COMPILE)as
  CC:=$(CROSS_COMPILE)gcc
  LD:=$(CROSS_COMPILE)ld
  OBJCOPY:=$(CROSS_COMPILE)objcopy
  
  CFLAGS:= -c -mcpu=arm926ej-s -g
  ASFLAGS:= -mcpu=arm926ej-s -g
  
  BIN_TARGET:=test.bin
  
  $(BIN_TARGET): $(C_OBJLIST) $(ASM_OBJLIST)
      $(LD) -T $(LD_SCRIPT) -o $@.elf $^
      $(OBJCOPY) -O binary $@.elf $@
  
  %.o: %.S
      $(AS) $(ASFLAGS) -o $@ $&lt;
  
  %.o: %.c
      $(CC) $(CFLAGS) -o $@ $&lt;
  
  clean:
      rm -f *.o *.elf *.bin
  </code></pre>
  
  <p>If handling multiple extensions in a single rule is possible, I can just use gcc for all source files instead of bothering to use as at all. (I guess)</p>