title: How is overflow detected at the binary level?
body: <p>I'm reading the textbook Computer Organization And Design by Hennessey and Patterson (4th edition). On page 225 they describe how overflow is detected in signed, 2's complement arithmetic. I just can't even understand what they're talking about.</p>
  
  <blockquote>
    <p>"How do we detect [overflow] when it <em>does</em> occur? Clearly, adding or
    substracting two 32-bit numbers can yield a result that needs 33 bits
    to be fully expressed."</p>
  </blockquote>
  
  <p>Sure. And it won't need 34 bits because even the smallest 34 bit number is twice the smallest 33 bit number, and we're adding 32 bit numbers.</p>
  
  <blockquote>
    <p>"The lack of a 33rd bit means that when overflow occurs, the sign bit
    is set with the <em>value</em> of the result instead of the proper sign of
    the result."</p>
  </blockquote>
  
  <p>What does this mean? The sign bit is set with the "value" of the result... meaning it's set as if the result were unsigned? And if so, how does that follow from the lack of a 33rd bit?</p>
  
  <blockquote>
    <p>"Since we need just one extra bit, only the sign bit can be wrong."</p>
  </blockquote>
  
  <p>And that's where they lost me completely.</p>
  
  <p>What I'm getting from this is that, when adding signed numbers, there's an overflow if and only if the sign bit is wrong. So if you add two positives and get a negative, or if you add two negatives and get a positive. But I don't understand their explanation.</p>
  
  <p>Also, this only applies to unsigned numbers, right? If you're adding signed numbers, surely detecting overflow is much simpler. If the last half-adder of the ALU sets its carry bit, there's an overflow.</p>
  
  <p>note: I really don't know what tags are appropriate here, feel free to edit them.</p>