Simulink Design Verifier

Using Existing Coverage Data during Subsystem Analysis



Measuring the Coverage of the Subsystem

The sldvdemo_autotranssldvdemo_autotrans model is a closed-loop simulation model. The subsystem ShiftLogicShiftLogic is a Stateflow® chart and represents the controller part of this model. Test cases designed in the Signal Builder block ManeuversGUIManeuversGUI drive the closed-loop simulation. You can use the cvtestcvtest and cvsimcvsim functions to measure the model coverage achieved for this subsystem inside the closed-loop simulation model. In this example, specifying the input to cvtestcvtest as a path to the subsystem rather than to the model name results in measuring the coverage for the subsystem only. Also, the second input to cvsimcvsim specifies the time interval to simulate the model and it is derived from the time range of the current pane in the block ManeuversGUIManeuversGUI.



test = cvtest('sldvdemo_autotrans/ShiftLogic');
test.settings.decision = 1;
test.settings.condition = 1;
test.settings.mcdc = 1;

signalBuilderBlock = sldvdemo_signalbuilder_block('sldvdemo_autotrans');
signalBuilderTime = signalbuilder(signalBuilderBlock);
simulationStopTime = signalBuilderTime{1,1}(end);

existingCovData = cvsim(test,[0 simulationStopTime]);
cvhtml('Existing Coverage', existingCovData);

Finding Test Cases for Missing Coverage

Before you can use existing coverage data during test generation, the data must be saved to a coverage data file(.cvt). You can use existing coverage data by specifying the coverage data path in the Coverage data file parameter and setting Ignore objectives satisfied in existing coverate data parameter to on in the Test Generation pane of Simulink Design Verifier configuration parameters.

In this demonstation, the first input to sldvrunsldvrun specifies the subsystem to analyze. Instructing Simulink Design Verifier to analyze a subsysyem is beneficial when the controller part of a model needs to be tested separately or when you want to divide the analysis of a large model into smaller, manageable parts.

As you can see in the report, Simulink Design Verifier only finds test cases for the coverage objectives that are not covered in the existing coverage file. Notice that 4 coverage objectives in the subsystem ShiftLogicShiftLogic are proven to be unsatisfiable. This is expected because the logic inside the Stateflow chart ShiftLogicShiftLogic uses temporal events and since this chart updates at every sample time, usage of temporal conditions should be satisfactory. Also note that, dead code within a subsystem will always be a dead code in the model containing that subsystem.

The harness model generated by Simulink Design Verifier is built by extracting the contents of the subsystem ShiftLogicShiftLogic into a Test Unit component that is fed by a Signal Builder block that captures the generated test cases.


opts = sldvoptions;
opts.IgnoreCovSatisfied = 'on';
opts.CoverageDataFile = 'existingcov.cvt';
opts.SaveHarnessModel = 'on';

[~, harnessModel] = fileparts(fileNames.HarnessModel);

Clean Up
