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By saratoga on 1/31/2007 3:47:21 PM , Rating: 2
The long pipeline of netburst made HT viable, parts of it were idling while others were busy - HT was just means to increase the load of the chip and thus its efficiency.

Length and width are what matters. A long pipeline, or a wide pipeline are both good for HT. A long, wide pipeline is best.

So, you're telling me that HT is of the same quality as SMT in a, lets say, Power5 series processor or a Sun T1?

Define "quality". Both are SMT, though the T1's is very different then the P4's (which was more like the POWER5's).

No, dont answer me.


Compared to these two examples, Intels HT is a whackjob. Its fallout from the netburst design - it was a logical consequence of the design, but not remotely close to a "true" SMT design such as the Power5 or T1.

Thats nonsense. Also, what is a "true" SMT design? I get the impression that you don't really understand how HT is implemented in the P4, based on your comparison to the T1.


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