A CMOS circuit includes a pair of N-doped regions, separated by aP-doped channel, as well as P-doped regions, separated by anN-doped channel. Although this forms PNP and NPN transistors,the bias of the regions is designed so the junctions are reversebiased and the electric field effects on the channel are supposedto control the MOS-FET transistors operations. There is afailure mode of a CMOS circuit where the bias conditions areviolated. What is the failure mode, what causes it, whateffects does it cause, and what is the simplest recovery mechanism.