def run(self, display=False, outputfile='a.out', include=None, define=None):
        if self.sim == 'iverilog' or self.sim == 'icarus':
            return self._run_iverilog(display, outputfile, include, define)
        if self.sim == 'modelsim' or self.sim == 'vsim':
            return self._run_modelsim(display, self.top, include, define)
        raise NotImplementedError(self.sim % "Not implemented: '%s'")
dataset/ETHPy150Open PyHDI/veriloggen/veriloggen/verilog/simulation.py/Simulator.run/swapped operands of `%`