def create_decl(self, sigtypes, name, width=None, length=None, lineno=0):
        self.typecheck_decl(sigtypes, length)
        decls = []
        signed = False
        if 'signed' in sigtypes:
            signed = True
        if 'input' in sigtypes:
            decls.append( Input(name=name, width=width, signed=signed, lineno=lineno) )
        if 'output' in sigtypes:
            decls.append( Output(name=name, width=width, signed=signed, lineno=lineno) )
        if sigtypes in 'inout':
            decls.append( Inout(name=name, width=width, signed=signed, lineno=lineno) )
        if 'wire' in sigtypes:
            if length:
                decls.append( WireArray(name=name, width=width,
                                        signed=signed, length=length, lineno=lineno) )
            else:
                decls.append( Wire(name=name, width=width, signed=signed, lineno=lineno) )
        if 'reg' in sigtypes:
            if length:
                decls.append( RegArray(name=name, width=width,
                                       signed=signed, length=length, lineno=lineno) )
            else:
                decls.append( Reg(name=name, width=width, signed=signed, lineno=lineno) )
        if 'tri' in sigtypes:
            decls.append( Tri(name=name, width=width, signed=signed, lineno=lineno) )
        if 'supply0' in sigtypes:
            decls.append( Supply(name=name,value=IntConst('0', lineno=lineno),
                                 width=width, signed=signed, lineno=lineno) )
        if 'supply1' in sigtypes:
            decls.append( Supply(name=name,value=IntConst('1', lineno=lineno),
                                 width=width, signed=signed, lineno=lineno) )
        return decls
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/vparser/parser.py/VerilogParser.create_decl/swapped operands of `in`