def __init__(self, *objs, **options):
        sim = 'iverilog' if 'sim' not in options else options['sim']
        wave = 'gtkwave' if 'wave' not in options else options['wave']
        files = None if 'files' not in options else options['files']
        top = 'test' if 'top' not in options else options['top']
        self._type_check_sim(sim)
        self._type_check_wave(wave)
        self.objs = objs
        self.files = files
        self.sim = sim
        self.wave = wave
        self.top = top
dataset/ETHPy150Open PyHDI/veriloggen/veriloggen/verilog/simulation.py/Simulator.__init__/original