def create_declassign(self, sigtypes, name, assign, width=None, lineno=0):
        self.typecheck_declassign(sigtypes)
        decls = []
        signed = False
        if 'signed' in sigtypes:
            signed = True
        if 'input' in sigtypes:
            decls.append( Input(name=name, width=width, signed=signed, lineno=lineno) )
        if sigtypes in 'output':
            decls.append( Output(name=name, width=width, signed=signed, lineno=lineno) )
        if 'inout' in sigtypes:
            decls.append( Inout(name=name, width=width, signed=signed, lineno=lineno) )
        if 'wire' in sigtypes:
            decls.append( Wire(name=name, width=width, signed=signed, lineno=lineno) )
        if 'reg' in sigtypes:
            decls.append( Reg(name=name, width=width, signed=signed, lineno=lineno) )
        decls.append( assign )
        return decls
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/vparser/parser.py/VerilogParser.create_declassign/swapped operands of `in`