def getFiniteStateMachine(self, termname, funcdict):
        fsm = FiniteStateMachine(util.toFlatname(termname))
        if len(funcdict) == 0: return fsm
        width = self.getWidth(termname)
        for condlist, func in sorted(funcdict.items(), key=lambda x:len(x[0])):
            if not isinstance(func, DFEvalValue): continue
            print("Condition: %s, Inferring transition condition" % str(condlist))
            node = transition.walkCondlist(condlist, termname, width)
            if node is None: continue
            statenode_list = node.nodelist if isinstance(node, transition.StateNodeList) else [node,]
            for statenode in statenode_list: fsm.construct(func.value, statenode)
        return fsm
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/controlflow/controlflow_analyzer.py/VerilogControlflowAnalyzer.getFiniteStateMachine/original