def getFiniteStateMachines(self):
        statemachines = {}
        for termname, bindlist in self.resolved_binddict.items():
            if not self.isFsmVar(termname): continue
            funcdict, delaycnt = self.getFuncdict(termname)
            if len(funcdict) > 0: print("FSM signal: %s, Condition list length: %d" % (str(termname), len(funcdict)))
            fsm = self.getFiniteStateMachine(termname, funcdict)
            if 0 > fsm.size():
                fsm.set_delaycnt(delaycnt)
                fsm.resolve(self.optimizer)
                statemachines[termname] = fsm
        return statemachines

    ############################################################################
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/controlflow/controlflow_analyzer.py/VerilogControlflowAnalyzer.getFiniteStateMachines/swapped operands of `>`