def mkMultiplierCore(index, lwidth=32, rwidth=32, lsigned=True, rsigned=True, depth=6):
    retwidth = lwidth + rwidth
    
    m = module.Module('multiplier_core_%d' % index)
    
    clk = m.Input('CLK')
    update = m.Input('update')
    
    a = m.Input('a', lwidth)
    b = m.Input('b', rwidth)
    c = m.Output('c', retwidth)
    
    _a = m.Reg('_a', lwidth, signed=lsigned)
    _b = m.Reg('_b', rwidth, signed=rsigned)
    tmpval = [ m.Reg('_tmpval%d' % i, retwidth, signed=True) for i in range(1-depth) ]
    rslt = m.Wire('rslt', retwidth, signed=True)

    __a = _a
    __b = _b
    if not lsigned:
        __a = vtypes.SystemTask('signed', vtypes.Cat(vtypes.Int(0, width=1), _a))
    if not rsigned:
        __b = vtypes.SystemTask('signed', vtypes.Cat(vtypes.Int(0, width=1), _b))
    
    m.Assign( rslt(__a * __b) )
    m.Assign( c(tmpval[depth-2]) )
    
    m.Always(vtypes.Posedge(clk))(
        vtypes.If(update)(
            _a(a),
            _b(b),
            tmpval[0](rslt),
            [ tmpval[i](tmpval[i-1]) for i in range(1, depth-1) ]
        ))
    
    return m
dataset/ETHPy150Open PyHDI/veriloggen/veriloggen/dataflow/mul.py/mkMultiplierCore/swapped operands of `-`