def add(self, srcs, dst, cond):
        sb, se = srcs
        for src in range(sb, se+1):
            if not src in self.fsm:
                self.fsm[src] = {}
            self.fsm[src][cond] = dst
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/controlflow/controlflow_analyzer.py/FiniteStateMachine.add/original