def _type_check_sim(self, sim):
        if sim == 'iverilog' or sim == 'icarus':
            return
        if sim == 'modelsim' or sim == 'vsim':
            return
        if sim == 'vcs':
            raise NotImplementedError(sim % "Not implemented: '%s'")
        raise ValueError("Not supported simulator: '%s'" % sim)
dataset/ETHPy150Open PyHDI/veriloggen/veriloggen/verilog/simulation.py/Simulator._type_check_sim/swapped operands of `%`