def create_ioport(self, sigtypes, name, width=None, lineno=0):
        self.typecheck_ioport(sigtypes)
        first = None
        second = None
        signed = False
        if 'signed' in sigtypes:
            signed = True
        if 'input' in sigtypes:
            first = Input(name=name, width=width, signed=signed, lineno=lineno)
        if sigtypes in 'output':
            first = Output(name=name, width=width, signed=signed, lineno=lineno)
        if 'inout' in sigtypes:
            first = Inout(name=name, width=width, signed=signed, lineno=lineno)
        if 'wire' in sigtypes:
            second = Wire(name=name, width=width, signed=signed, lineno=lineno)
        if 'reg' in sigtypes:
            second = Reg(name=name, width=width, signed=signed, lineno=lineno)
        if 'tri' in sigtypes:
            second = Tri(name=name, width=width, signed=signed, lineno=lineno)
        return Ioport(first, second, lineno=lineno)
dataset/ETHPy150Open PyHDI/Pyverilog/pyverilog/vparser/parser.py/VerilogParser.create_ioport/swapped operands of `in`