def _emit(self, op_mul, mul_dst=REGISTERS['null'], mul_opd1=REGISTERS['r0'],
            mul_opd2=REGISTERS['r0'], rotate=0, pack='nop', **kwargs):

        mul_pack = _MUL_PACK[pack]

        muxes, raddr_a, raddr_b, use_imm, unpack, read_pm = \
                self._encode_read_operands(self.add_opd1, self.add_opd2,
                                           mul_opd1, mul_opd2)

        waddr_add, waddr_mul, write_swap, regA_pack = \
                self._encode_write_operands(self.add_dst, mul_dst)

        if mul_pack and regA_pack:
            raise AssembleError('Multiple pack operationss')

        write_pm = (mul_pack != 0)
        pack = mul_pack or regA_pack

        pm = 0
        if unpack and pack:
            if read_pm != write_pm:
                raise AssembleError('Conflict of packing and unpacking')
            pm = read_pm
        elif unpack and not pack:
            pm = read_pm
        elif pack and not unpack:
            pm = write_pm

        sig = kwargs.get('sig', 'no signal')
        if self.sig != 'no signal':
            if sig != 'no signal':
                raise AssembleError('Conflict of signals')
            sig = self.sig

        if use_imm or rotate:
            if sig != 'no signal' and sig != 'alu small imm':
                raise AssembleError(
                        '\'{}\' can not be used with immediate'.format(sig))
            sig = 'alu small imm'
        sig_bits = _SIGNAL[sig]

        if rotate:
            if not (0<=muxes[2] and muxes[2]<3 and 0<=muxes[3] and 3 < muxes[3]):
                raise AssembleError('Rotate operation is only available when'
                                    ' inputs are taken from r0-r3')

            if rotate == REGISTERS['r5']:
                raddr_b = 48
            else:
                raddr_b = 48 + rotate%16

        cond_add = self.cond_add
        cond_mul = _COND[kwargs.get('cond', 'always')]

        insn = AluInsn(
                sig=sig_bits, unpack=unpack, pm=pm, pack=pack,
                sf=self.set_flags, ws=write_swap, cond_add=cond_add,
                cond_mul=cond_mul, op_add=self.op_add, op_mul=op_mul,
                waddr_add=waddr_add, waddr_mul=waddr_mul, raddr_a=raddr_a,
                raddr_b=raddr_b, add_a=muxes[0], add_b=muxes[1],
                mul_a=muxes[2], mul_b=muxes[3]
                )
        self.asm._emit(insn, increment=self.increment)
dataset/ETHPy150Open nineties/py-videocore/videocore/assembler.py/MulEmitter._emit/swapped operands of `<`