VHDL Array Type Case Handling
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Lets consider the following (and ignore synthesis for the moment):

    SIGNAL sig1 : std_logic_vector( 3 DOWNTO 0 ) := "0000";

    CASE sig1 IS

        when "0000" => do something
        when "0001" => do something
        when others => do something

    END CASE;

I know that is very good practice to have a conditional for each potential "valid" value of sig1 ( "0000", "0001", "0010", ..., "1111" ) because the others check would include 'U', 'X', and 'Z'.  So, this good practice tells us that the example above is not good VHDL code.

Now lets consider the following (keeping synthesis in mind):

    TYPE state_type IS ( state0, state1, state2, state3, state4 );

    SIGNAL sig2 : state_type;

    CASE sig2 IS
        when state0 => do something
        when state1 => do something
        when state3 | state4 => do something
        when others => do something
    END CASE;

The same action would be taken state3 and state4 have the same action.  The intent for others is to have the same action for states 2 and 5.  

Is it still "required" to do something similar to the follow

    when state2 | state5 => do something
    when others => null;

My goal is to avoid having to have a huge list of states OR'd together for the same action.

Thanks!