Setting Variables within Makefile commands
===

I'm facing a silly problem with GNU makefile.
I want to define two targets to build a c program; one with debugging and the other without.

    runNoDebug: setNoDeb objs runMe
    
    runDebug: setDeb objs runMe
    
    setNoDeb:
         {EXPORT} MyDEBUG= -O3
    
    setDeb:
         {EXPORT} MyDEBUG="-DDEBUG=1 -g"
    
    objs: cFiles
        $(CC) -o $@ $^ $(cFiles) $(CFLAGS) $(LIBS) $(MYDEBUG)
    
    runme: objs
        ./oo

Errors arise on running this makefile, the command to set debugging executes on the subshell causing errors. If "Export" is added, the variable is defined in that subshell.

I want to define this variable in the makefile iteself to be used while building objects.

Is it possible? Or should I duplicate the "objs: cFiles" target?